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題名 | Exploring the Design Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems=快取記憶體,資料匯流排寬度,及爆發式傳送記憶體設計空間之探討 |
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作者 | 陳中和; Chen, Chung-ho; |
期刊 | 中國工程學刊 |
出版日期 | 19980500 |
卷期 | 21:3 1998.05[民87.05] |
頁次 | 頁269-282 |
分類號 | 471.651 |
語文 | eng |
關鍵詞 | 快取記憶體; 資料匯流排寬度; 爆發式傳送記憶體; 效益評量; Burst transfer memory; Cache system; Data path; Die area; Performance tradeoffs; |
中文摘要 | 快取記憶體,資料匯流排寬度,爆發式傳送記憶體三者為降低處理器與主 記憶體資料傳遞時間之主要硬體技術。本文以一評量方法探討快取記憶體命中 率,資料匯流排寬度,及爆發式傳送記憶體三者之效能關係。我們的結果顯示 如果一個資料匯流排為D位元組寬的系統與一資料匯流排寬為2D位元組的系 統有同樣的效能,則換取資料匯流排D位元組寬之效能之快取記憶體命中率介 於0(低限)到1-HR(高限)之間。其中HR為資料匯流排為D位元組寬的系 統之快取記憶體命中率。就目前受傳送時間主宰之主記憶體而言,加倍資料匯 流排寬度之效益大約換取上述高限的一半。加倍資料匯流排寬度之好處以微處 理器搭配高速之L2快取記憶體較為有利。若系統有相當大量之非快取記憶體 存取動作,則加倍資料匯流排寬度可換取相當大之快取記憶體命中率。 |
英文摘要 | Caches, data path, and burst transfer memory are the major hardware techniques used to reduce the latency between the pocessor and the main memory. We explore the design space among the hit ratio (hence a cache size, or an improved cache structure), data path width, and the transfer memory design through a performance tradeoff methodology. For the tradeoffs among these three factors, our evaluation shows that if a D-byte data path system and a 2D-byte data path system have the same performance, then the hit ratio difference that trades the performance of a D-byte wide data path is between 1(low bound) and 1-HR (high bound) where HR is the hit ratio associated with the D-byte system. For current main memory systems, doubling the data path trades about half of the high bound of the hit ratio traded in a transfertime dominated system. Doubling the data bus is more advantageous when the processor is designed with the use of a high-speed non-comstant- time-dominated L2 cache. Doubling the bus width trades a large percentage of the hit ratio when a large amount of non-cacheable 2D- byte memory traffic exists. |
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