查詢結果分析
相關文獻
- 乘法器的IC設計
- The Design and Implementation of a Pipelined Multiplier Associated with a New Pass Transistor Asynchronous Control Unit
- An Expansible Fixed-Point Multiplier
- 利用改良的記憶體壓縮法和函數分離法設計餘數數字系統中的乘法器
- Large Signal Analysis of Low-Voltage BiMOS Analog Multipliers Using Fourier-Series Approximations
- A Uniform VLSI Architecture for Modulo n Adder/Subtracter and Multiplier
- 快速捲積運算之高效能VLSI設計
- A Four-Quadrant Multiplier Circuit Based on Current Followers
- 低電壓CMOS類比四象限乘法器之設計與研製
- 乘法電路產生器設計
頁籤選單縮合
題 名 | 乘法器的IC設計=IC Design of Multiplier |
---|---|
作 者 | 謝慶發; 廖鴻儒; 簡靜珊; | 書刊名 | 中華技術學院學報 |
卷 期 | 28 2003.10[民92.10] |
頁 次 | 頁193-201 |
分類號 | 448.595 |
關鍵詞 | 全客戶設計; 乘法器; 方位比; Full-custom design; Multiplier; Aspect ratio; |
語 文 | 中文(Chinese) |
中文摘要 | 在本文中,我們使用TSMC0.35微米、2P/4M、混合模式、3.3/5V的製程資料以全客戶設計之方法設計一個乘法器。 依據文獻上之資料,有多種不同乘法器之架構,如Baugh-Wooley乘法器,陣列乘法器,序並行乘法器...等,此處我們採用最基本最直接的乘法運算過程去實現我們的乘法器,此乘法器由幾種基本邏輯閘構成,對每個邏輯閘我們調整其方位比,以得到適當之特性,並把它叫做基本細胞,在基本細胞被設計以後,我們用它來設計半加器、全加器和乘法器,所有電路均以HSPICE模擬驗證無誤,佈局、設計規則檢驗和電路佈局比對則以VIRTUOSO和CALIBRE完成。 |
英文摘要 | In this paper, we provide a method to implement an integrated circuit of multiplier, a full-custom design, with TSMC 0.35μm, 2P/4M, mixed-mode, 3.3/5V-roocess technology. Different from the design methods of others kinds of multipliers (such as the Baugh-Wooley multiplier, the array multiplier, and the serial-parallel multiplier), we use the basic multiplication to design our circuit, which is composed by several basic logic gates. For each gate, which is called the basic cell, we adjust its aspect ratio to derive proper characteristics. Then, the half-adder, and the multiplier are designed based on those basic cells. Finally, all the circuits and layouts are simulated and verified by the HSPICE,VIRTUOSO and CALIBRE. |
本系統中英文摘要資訊取自各篇刊載內容。