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題名 | 低電壓CMOS類比四象限乘法器之設計與研製=Design and Implementation of Low Voltage CMOS Four-Quadrant Analogue Multiplier (4-QAM) |
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作者 | 李世明; | 書刊名 | 國立雲林技術學院學報 |
卷期 | 6:3 1997.07[民86.07] |
頁次 | 頁339-345 |
分類號 | 448.5 |
關鍵詞 | 類比四象限乘法器; Analog four-quadrant multiplier; |
語文 | 中文(Chinese) |
中文摘要 | 本論文提出利用規則堆積式架構中二個線性區的金氧半電晶體來完成一低電壓互補金氧半類比四象限乘法器,此電路可在低電壓± 1.5V的電源下操作,在其直流差動輸入電壓± 0.8V範圍內,其非線性誤差少於0.9 %,總諧波失真(Total Harmonic Distortion,THD)低於1%,且-3dB頻寬可達近 15MHz 的範圍,直流消耗功率只有24.4mW。此晶片之研製是採用臺積 TSMC 0.8 μ m SPDM N-Well的製程,實際晶片面積約為251 × 653 μm�插C |
英文摘要 | A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of ± 1.5V. For a differential input voltage range up to ± 0.8V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB bandwidth of this multiplier is about 15MHz. The chip was fabricated in TSMC 0.8 μm SPDM N-well process. The chip dissipates 24.4mW and occupies 251 × 653 μm�� active area. |
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