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題名 | 快速捲積運算之高效能VLSI設計=A High Performance VLSI Design of Fast Convolution Computation |
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作 者 | 許明華; 林蘇宏; | 書刊名 | 科技學刊 |
卷期 | 9:4 2000.10[民89.10] |
頁次 | 頁263-268 |
分類號 | 448.57 |
關鍵詞 | 捲積運算; 餘數系統; 分散式數學演算法; 餘數乘法器; Convolution computation; Residue number system; Distributed algorithm; Modular multiplier; |
語文 | 中文(Chinese) |
中文摘要 | 捲積運算(Convolution)為數位信號處理技術(DSP)中常見的運算處理。在本 篇論文中,我們將以餘數系統(RNS)[1]及分散式數學演算法(DA)[2]的特性來實現快速 捲積運算的設計。在餘數系統中資料在運算時,所有的進位結果都不會影響運算的進行,因 此並沒有進位延遲(Carry-Delay)的考量,分散式數學演算法能實現利用資料位元串列輸 入,經由記憶體查表法有效率地簡化捲積運算中的乘法處理。在數學演算法的推導流程中, 以提升整體運算速度以及面積的最佳化為設計方向提出新的VLSI架構。另外輸入資料及輸出 結果不必經由額外的值域轉換電路,就可以在餘數系統的值域裡完成運算。最後整個積體電 路的面積為420um*600um,工作頻率為66MHz。 |
英文摘要 | Convolution computation is a general arithmetic operation in DSP technology. In this paper, an efficient and effective convolution hardware architecture is presented by using both characteristics of residue number system and distributed arithmetic algorithm. With exploiting the arithmetic algorithm, we develop a new VLSI architecture, which can speed up the convolution operation and optimize the cost of circuit design. There are three main merits in our architecture: (1)it has no result of carry propagation delay for all data computation in the hardware circuit, (2)the hardware complexity of multiplication can be reduced simplifying look-up table, and (3)the input data does not need a converter to transfer binary value to residue number. Finally, the chip layout of the presented architecture has been implemented by 0.6 um CMOS technology. The chip area is 420um*600um and the transistor count is 1005. Its maximum working frequency is 66MHz. |
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