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題 名 | 應用於通訊系統之GHz低功率鎖相迴路研究=GHz Low-Power Phase-Locked Loop Design for Communication System |
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作 者 | 余森年; 張志銘; | 書刊名 | 中州學報 |
卷 期 | 22 民94.12 |
頁 次 | 頁159-169 |
分類號 | 448.532 |
關鍵詞 | 鎖相迴路; 相位頻率偵測器; 充電幫浦; 電壓控制振盪器; 除頻器; Phase-locked loop; Phase-frequency detector; Charge pump & low pass filter; Voltage controlled oscillator; Frequency divider; |
語 文 | 中文(Chinese) |
中文摘要 | 鎖相迴路在VLSI的領域中應用極為廣泛,已成為不可或缺的基本元件。隨著VLSI製造技術不斷地進步,目前的鎖相迴路除特殊用途之外,大部分均是單晶片系統設計。而隨著可攜式電子產品的大幅應用,功率消耗變為主要的考慮,故本研究主要在提出低功率的鎖相迴路。本研究以TSMC0.35μm2p4m的製程、工作電壓為3V條件下,以Hspice進行鎖相迴路設計與模擬,由模擬的結果顯示,鎖住1GHZ的功率消耗為12.4mW,本研究功率消耗及相位誤差方面,能達到不錯的效果。 |
英文摘要 | Phase-locked loop (PLL) is the component broadly used in various field of integrated circuits. Owing to the broadly use of the mobile electronic systems, product with small size and low power consumption are the more and more important. Due to the improvement of VLSI technology, phase locked loop can be designed in system on a chip (SOC). The goal of the paper is to design a phase-locked loop circuit with low power consumption. In the paper, the authors develop a PLL, that the source voltage is 3V and based on TSMC 0.35um 2p4m technology. The simulated results of the proposed method by Hspice indicates that, the power consumption is 12.4mW at 1 GHz. The results show the outstanding performance of the proposed method in power consumption and phase error. |
本系統中英文摘要資訊取自各篇刊載內容。