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題 名 | 低電壓CMOS鎖相迴路於脈波產生器之設計研究=Research on the Design of Low Voltage CMOS Phase Locked Loops for Clock Generator |
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作 者 | 李宏斌; 鍾文耀; | 書刊名 | 中原學報 |
卷 期 | 29:3 2001.09[民90.09] |
頁 次 | 頁293-301 |
分類號 | 448.57 |
關鍵詞 | 低電壓CMOS鎖相迴路; 相頻偵測器; 電荷充電泵; 壓控振盪器; 迴路濾波器; 除頻器; 環振盪器; Phase locked loop; Phase frequency detector; Charge pump; Loop filter; Divider and ring oscillator; |
語 文 | 中文(Chinese) |
中文摘要 | 本論文主要在進行一應用於脈波產生器之低電壓CMOS鎖相迴路的設計研究。此電路主要是利用電荷充電葉之核心概念設計,其關鍵電路方塊由相頻偵測器﹒、電荷充電菜、壓控振盪器、迴路濾波器,及除頻器所組成。 為提高鎖相迴路抗雜訊及對溫度穩定之性能需求,本論文之相頻偵測器是採用可消除盲帶區雜訊影響的預充電架構來實現,而電荷充電茱所使用的定電流源為可對溫度作補償的熱電壓參考電路,另外在數位雜訊的避免上也使用了非重疊電路作補償,壓控振盪器的部分使用了環振盪器,每一級皆使用差分輸入及差分輸出的放大器以避免抖動雜訊的發生。在迴路濾波器的部分,利用二階的系統以濾除相頻偵測器與電荷充電褒所產生的高頻雜訊,同時降低電壓跳動對壓控振盪器的影響。本研究採用並聯電容值之調整以求穩定度及足夠之相角限,除頻器兼具有除頻與輸出緩衝器之功能。本文所設計之鎖相迴路採用台灣積體電路製造公司0.35μm1P4M製程來實現,佈局面積為 767.7μm*305μm'其規格為2.7V-3.3V電源操作下, 6MHz輸入訊號,可產生12M Hz 、24MHz、48MHz與96MHz四個訊號輸出選擇,其壓控振盪器最大頻率為125M施,預估的抖動為72Ops'最大功率消耗為lOmW0本電路成果適合於系統晶片之頻率 合成器與微處理器時序產生等應用。 |
英文摘要 | The aim ofthis thesis is to design a low voltage CMOS phase locked loop (PLL) for c10ckgenerator applications. The charge pump concept has been used in the PLL implementation and the core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter and divider. This thesis adopts some methods below in order to improve the noise and stability performance of the PLL. Firstly, the frame of pre-charge stage is used to eliminate the noise of dead】zone in phase frequency detector. Secondly, the VT reference circuit has been used to design constant current source in charge pump for temperature compensation, and the non-overlapping circuit is used to reduce the digital noise from the timing mismatch. The ring oscillator using fully differential input and output stage in voltage-controlled oscillator prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. The magnitude changing of parallel capacitor is used for obtaining enough phase margins. The divider provides both functions on frequency division and the output buffer for phase locked loop. The chip has been implemented in the TSMC 0.35μm lP4M CMOS technology and the core layout area is 767.7μm * 305μm. For 2.7 to 3.3V power supply, the input frequency is 6 M Hz, and the output frequencies are 12 M Hz, 24M Hz, 48M Hz, and 96MHz. The results show the jitter is 720ps at 6 MHz and the maximum power consumption is lOmWat 3V power supply. The proposed PLL has been shown its performance can be used in c10ckgenerator and frequency synthesizer applications. |
本系統中英文摘要資訊取自各篇刊載內容。