查詢結果分析
相關文獻
- A High-Speed Systolic Array Architecture for LZSS Data Compression System
- A Memory-Based Approach to the Design of Efficient VLSI Arrays for the Multi-dimensional Discrete Hartley Transform
- 一個適用於近似週期信號的新自適性向量量化法及其在心電圖資料壓縮上的應用
- 具有Super-filling現象的電鍍銅技術與其在超大型積體電路中的應用
- VLSI Architecture for Iteration-Free Fractal Image Decoding
- 低耗電積體電路設計技術之探討
- Data Compression Techniques for Chinese Character Patterns
- 光電互連系統之直接晶片鍵合技術
- Design of VLSI Parallel Processors for Hough Transform-Based Line Detection
- 多階層式無失真資料壓縮晶片設計
頁籤選單縮合
題名 | A High-Speed Systolic Array Architecture for LZSS Data Compression System=應用於高速率LZSS壓縮系統之心脈收縮陣列式架構 |
---|---|
作者 | 陳晉明; 魏哲和; | 書刊名 | Journal of the Chinese Institute of Electrical Engineering |
卷期 | 6:4 1999.11[民88.11] |
頁次 | 頁271-284 |
分類號 | 448.5 |
關鍵詞 | 資料壓縮; 超大型積體電路; 心脈收縮陣列; LZ77壓縮法; LZ78壓縮法; Data compression; VLSI; Systolic array; LZ77; LZ78; |
語文 | 英文(English) |
中文摘要 | 本論文提出一種應用於高速率 LZSS 壓縮系統之心脈收縮陣列式架構。當新的未 編碼字串進入本系統時,此壓縮系統可藉一連串的編碼細胞單元陣列,在已編碼字串中尋找 最大長度之相同字串,並加以編碼及壓縮。有效率的硬體實現架構,不僅提高了系統壓縮速 率,而且降低硬體實現的複雜度與成本。 新的設計方式, 使得本系統在 0.5 微米的 CMOS 製程下,能夠以 15ns 的操作時脈, 達成每秒 556 百萬位元之高速壓縮速率,進而滿足即 時通信需求。 |
英文摘要 | In this paper, we present a high-speed Ziv-Lempel (LZ type) data compression enconding system based on systolic array architecture. This encoding system employs a series of encoding cells to concurrently find the matches between each inpute data character and the encoded characters stored in the sliding windows. These matches will be encoded into a series of optimal codewords, which have been compressed. This compressor can easily achieve an ideal compression ratio by cascading the chips of the encoding cell. An efficient implementation of the LZSS compression technique is proposed to improve the encoding speed and reduce hardware complexity for the encoding cells. This new architecture requires a lower gate count than other high-speed LZ systems. This new approach can find a maximum match length for each clock cycle. Hence, the encoder encodes one character (more than 8 bits) per clock cycle, and its clock rate can be constrained below 10ns based on the Verilog simulation with 0.5um VLSI technology. Thus, the new hardware structure can execute the data compression task on-the-fly, and is very suitable for application in real-time communication systems. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。