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題名 | VLSI Architecture for Iteration-Free Fractal Image Decoding=免疊代碎形影像解碼器之超大型積體電路架構設計 |
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作者 | 張軒庭; 郭鐘榮; | 書刊名 | Journal of the Chinese Institute of Electrical Engineering |
卷期 | 6:3 1999.08[民88.08] |
頁次 | 頁259-269 |
分類號 | 448.57 |
關鍵詞 | 碎形; 超大型積體電路; 免疊代; 縮小性相似轉換; 管線化; Fractal; VLSI architecture; Iteration-free; Hardware complexity; Pipeline; |
語文 | 英文(English) |
中文摘要 | 傳統的碎形影像解碼方式需用到疊代過程,因此在硬體的製作較為複雜。為了解 決此一問題,我們基於所提出的一個免疊代解碼法則設計出其超大型積體電路架構。在此架 構中,我們沒有到一個乘法器,因為在縮小性相似轉換中的乘法運算已經被轉換成加法及移 位運算了,而區塊平均值則是利用移位運算達成,像素重組運算則是利用多工器及加法運算 完成。因此,此電路之硬體複雜度極低,我們還利用管線化程序來進一步加速解碼過程。電 腦模擬顯示我們所提出的架構具有及高速的靜態影像解碼速度,例如對一張512×512,八 位元/像□素的灰階影像,在10MHz的時脈波之下,只需要9×10□秒即可解碼完畢。此外, 在對不同格式的影像序列上,例如QCIF,CIF,CCIR601,及HDTV等,也有相當不錯表 現。 |
英文摘要 | Original fractal decoding requires iteration processing and hence complicates hardware implementation of the decoder. To overcome this problem, we design a VLSI architecture for the decoder based on a proposed iteration-free design for the fractal image codes. In the proposed architecture, no multiplier is required. The multiplication in the non-contractive affine transformation is replaced by summation and shifting operations. The averaging operation for determining the domain block mean is done with a shifter. On the other hand, the isometry operation can be achieved by multiplexing and summation operations. The hard-ware complexity is low and the pipeline arrangement is utilized to funther improve the decoding speed. The computer simulation shows that the proposed architecture can achieve fast decoding of still images. Suppose that a 512×512, 8 bit/pixel, gray –scale image is partitioned into 8×8 blocks, by using the proposed VLSI architecture the decoding time is only 9×10□ seconds based on a 10 MHz clock rate. Furthermore, the performance when decoding image sequences with formats such as the QCIF, CIF, CCIR601, and HDTV is also very high. |
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