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| 題 名 | A Memory-Based Approach to the Design of Efficient VLSI Arrays for the Multi-dimensional Discrete Hartley Transform=以記憶體為基礎而針對多維離散哈特利轉換之超大型積體電路陣列設計方法 |
|---|---|
| 作 者 | 郭峻因; | 書刊名 | Proceedings of the National Science Council : Part A, Physical Science and Engineering |
| 卷 期 | 23:2 1999.03[民88.03] |
| 頁 次 | 頁289-302 |
| 分類號 | 448.57 |
| 關鍵詞 | 記憶體; 多維離散哈特利轉換; 超大型積體電路陣列設計方法; Discrete hartley transform; Cyclic convolution; Memory-based implementation; |
| 語 文 | 英文(English) |
| 中文摘要 | 多維離散哈特利轉換的設計遭遇兩個困難點:一為其演算法上各維之運算無法先 行分開計算;二為其超大型積體電路陣列設計時功能單元實現。多維離散哈特利轉換的演算 法上各維之運算無法先行分開計算的特性造成在以超大型積體電路陣列實現時需要相當大的 額外成本,而功能單元的實現直接影響了所設計架構的性能表現。為了克服這些困難點;本 論文提出一個以記憶體為基礎的方法,針對多維離散哈特利轉換來設計其超大型積體電路陣 列。此方法推導出一個多維離散哈特利轉換的新公式,使得我們可以避免現有設計中所不希 望擁有的額外代價。此外,本論文所提出的方法可以將任何長度之多維離散哈特利轉換轉成 迴旋式公式,並將此公式以心縮式陣列實現,而且以小容量的唯讀記憶體及加法器來完成運 算之執行,這即是本文中所提的以記憶體為基礎之實現方法。利用迴旋式公式演算法可得到 高計算平行度與低計算複雜度的優點,採用心縮式陣列設計可得到高計算速度、低輸入╱輸 出代價及適合 VLSI 實現之優點,而採用記憶體為基礎的實現方法可以減少相當大的硬體實 現代價。此實現方式比分散式算術( DA )技巧更能節省硬體代價。總之,本論文所提出之 以記憶體為基礎的設計方法能夠提供在設計多維離散哈特利轉換電路時一個非常有效率的 VLSI 實現方法。 |
| 英文摘要 | The design of the multi-dimensional (M-D) discrete Hartley transform (DHT) involves two fundamental difficulties: the inseparability of the M-D DHT and the implementation of function units in very large scale integration (VLSI) architectures. The inseparability of M-D DHT yields much overhead in VLSI implementation, and the implementation of function units directly influences the performance of the designed architectures. To conquer these difficulties, in this paper, we present a memory-based approach which can be used to design efficient VLSI arrays for the M-D DHT. This approach derives a new formulation for the M-D DHT such that we can eliminate the undesirable overhead needed in former designs. Moreover, the presented approach can formulate the M-D DHT with any length as a cyclic convolution, realize it by means of a systolic array, and implement it using small read only memory (ROM) and adders, which are designated as memory-based implementation. Using cyclic convolution provides the advantages of high computing parallelism and low computation complexity. Using systolic array realization results in high computing speeds. low input/output (I/O) cost, and high feasibility for VLSI implementation. Adopting the memory-based implementation greatly reduces the hardware cost. This implementation scheme is more hardware-efficient than the well-known distributed arithmetic (DA) technique. To sum up, the presented memory-based design approach will lead to efficient VLSI implementation of M-D DHT. |
本系統中英文摘要資訊取自各篇刊載內容。