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| 題 名 | Integrate Stream Buffer and 2 Level Cache=整合線型緩衝記憶體與第二層快取記憶體 |
|---|---|
| 作 者 | 張維君; | 書刊名 | 筧橋學報 |
| 卷 期 | 5 1998.09[民87.09] |
| 頁 次 | 頁77-88 |
| 分類號 | 471.65 |
| 關鍵詞 | 快取; 線型緩衝器; 記憶體時間; 記憶體架構; 模擬器; 先進先出; 最近使用; 快取擊中; 快取未擊中; Cache; Stream buffer; Memory latency; Memory hierarchy; Simulator; FIFO; LRU; Cache hit; Cache miss; |
| 語 文 | 英文(English) |
| 中文摘要 | 為了達到縮短記憶體與中央處理器性能上的差距，有效率的記憶體設計已引起廣 泛的興趣。一項較流行的解決方法，是採用階層式的記憶體設計，階層式的設計採用記憶體 獨特的位置及價格╱性能比之優點，經由程式行為分析之結果，絕大部份的程式於存取記憶 體時具有重覆位置的特色，這項分析引發我的記憶體架構設計。傳統式的記憶體架構以二層 快取及主記憶體組合而成，其重點在於價格╱性能比，這意謂著性能要有所提升，則付出的 代價相對地提高。一項使用簡單的線型緩衝器來調節價格昂貴的Ｌ２快取被提出，但此改革 設計只適用於具有規律性記憶體存取型態及大型資料集的應用程式；我的記憶體架構設計結 合上述二項之設計，預期開發出有效之利益。本計畫採用 ATOM 來模擬記憶體架構，並選用 SPEC95 的四個整數、六個浮點測試程式作為效能評估之依據， 本計畫之所以能有較佳的表 現乃在於整合線型緩衝器與Ｌ２快取，所以本計畫對大多數的工作能有好的表現。 |
| 英文摘要 | The possibility of shrinking the gap between memory access latency and processor cycle time has generated wide interest in designing effective memory hierarchy. A popular solution to match this requirement is levelage memory [Hennessy, 1996]. Levelage memory takes advantage of locality and cost/preformance of memory system. Analzing the program behavior, we find that most programs have locality characteristic [Hennessy, 1996] which involve the memory hierarchy mechanism. The conventional memory hierarchy is two levels cache and main memory. Since fast memory is expensive, the tradeoff of this model is cost/performance. An alternative hierarchy is suggested by using the simple stream buffer [Jouppi, 1990] to replace expensive the L2 cache [Palacharla, 1994]. The limitation of the stream buffer is that it works well only with applications which have regular access pattern or large data set size. My menory hierarchy design combines the stream buffer with the L2 cache to exploit the benefit of cost/performance of memory system. I use ATOM to generate my cache model simulator. I selected four integer and six floating point benchmarks from the SPEC 95 suites [SPEC, 95] in my evaluation. The reasons that my memory model can get better preformance are the advantage of stream buffer for scientific applications and the reduced size of L2 cache, but the model still can deal with the applications which have irregular access pattern. Hence, this cache model can work well for most workloads. |
本系統中英文摘要資訊取自各篇刊載內容。