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題 名 | 輸入緩衝電路的設計=Design of the Novel Input Buffer Circuits |
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作 者 | 陳宏仁; 蕭明椿; | 書刊名 | 樹德學報 |
卷 期 | 22 1999.02[民88.02] |
頁 次 | 頁59-69 |
分類號 | 448.532 |
關鍵詞 | 輸入緩衝器; 電壓擺幅; 入射; 臨限電壓; 過電壓應力; 靜態漏電流; Input buffer; Voltage swing; Undershoot; Threshold voltage; Over-voltage stress; Static leakage current; |
語 文 | 中文(Chinese) |
中文摘要 | 輸入緩衝電路的設計係首創有關於一種輸入信號正負電壓擺幅(+VDD至-VDD)或是具 入射電壓(-VDD)之CMOS輸入緩衝電路,其主要特徵為:該輸入緩衝電路設計有一PMOS型電壓變 換用電晶體MP2,其係連接在輸入信號與習知反相器電路之間,並將其閘極連接至接地節點 GND,俾將例如-3V電壓準位之輸入信號上拉至︱ VTP2︱ 之電壓準位後,方輸入至習知之反相 器電路,因此輸入緩衝電路中之各電晶體元件並無過電壓應力之情事發生;同時,該輸入緩衝 電路亦設計有一NMOS型開關控制用電晶體MN2,其係連接在習知反相器電路中之NMOS電晶體 與接地節點GND之間,並將其閘極連接至輸入節點IN,俾將輸入信號為例如-3V電壓準位時, 可藉該呈完全截止狀態之NMOS型開關控制用電晶體MN2,而有效消除靜態漏電流流通之問題, 藉此亦可有效抑制靜態漏電流之產生。 |
英文摘要 | A novel input buffer with input signal having positive and negative voltage swing or undershoot has been developed. The feature of the input buffer is that there is a PMOS pass transistor MP2 between input signal and the conventional CMOS inverter circuit. The gate of MP2 transistor is connected to ground node, so that the input voltage level of –3V could be pulled up to the absolute value of MP2 threshold voltage. This can efficiently remedy the over-voltage stress in the conventional CMOS inverter circuit. Moreover, there is also a NMOS switching transistor MN2 between the conventional CMOS inverter circuit and ground node. The gate of MN2 is connected to the input signal, so that the MN2 switching transistor will be fully off when the input voltage level of –3V is applied. This can greatly inhibit the static leakage current in the conventional CMOS inverter circuit. |
本系統中英文摘要資訊取自各篇刊載內容。