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| 題 名 | 新型CMOS互補式電流鏡反相放大器低電壓控制環形振盪器晶片之設計與研製=The IC Design and Chip Implementation of a New Low Voltage-Controlled Ring Oscillator Using a CMOS Complementary Current Mirror Inverter |
|---|---|
| 作 者 | 李世明; | 書刊名 | 技術學刊 |
| 卷 期 | 12:2 1997.06[民86.06] |
| 頁 次 | 頁285-292 |
| 分類號 | 448.5 |
| 關鍵詞 | 互補式電流鏡反相器; 電壓控制振盪器; Complementary current mirror inverter; CCMI; Voltage controlled oscillator; |
| 語 文 | 中文(Chinese) |
| 中文摘要 | 本研究主要是採用PMOS-NMOS互補式反相器(Complementary Inverter, CI),和電 流鏡 (Current Mirror), 組成之互補式電流鏡反相器 (Complementary Current Mirror Inverter, CCMI) 電路的架構來設計電壓控制振盪器 (Voltage Controlled Oscillator, VCO)。互補式電流鏡反相器有很大的頻寬,且有較小的延遲時間和較小增益,反之,互補反 相器有較高的增益,卻有較大的延遲時間,由於本文採用三級 CCMI 電路組成串聯的環式振 盪器,亦即由輸出端再取一回授信號接到輸入端,以形成無需輸入脈波信號而能形成自給偏 壓振盪的效應,因此振盪的頻率主要依靠於反相器串接的級數,負載電容和電流的大小。此 振盪器電路是採用國科會「晶片實現中心」所提供 0.8 μm CMOS SPDM 的製程來研製晶片 。本電路的設計是主要工作在次臨界區,在控制電壓 0.49V ∼ 0.65V 的範圍內,在無負載 時,其振盪頻率可由 2MHz 變化至 46MHz;當負載為 10pF 和 20pF 時,其頻率變化範圍分 別是 150kHz ∼ 3MHz 和 140kHz ∼ 2MHz。 本電路最大功率消耗約為 16.8 μw,晶片面 積約 280 μm× 150 μm。 |
| 英文摘要 | This research aims to design a low voltage controlled oscillator using a Complementary Current Mirror Inverter (CCMI). The complementary in verter with current mirrors, a rather new type of high-speed logic, has a larger bandwidth, a small time delay but a low gain, whereas complementary inverters have a high gain but a large time delay. A ring oscillator is realized using a three-stage CCMI, where the output of the last stage of the serially connected CCMI is fed back into the input stage. The frequency of self oscillation without adding extra input voltages depends on the mumber of inverter stages. The chip was fabricated in 0.8 μm CMOS Single Poly Double Metal (SPDM) process provided by the Chip Implementation Center (CIC). The proposed circuit is primarily operated in the MOS subthreshold region. The oscillating frequency varied from 2HMz to 46 MHz when controlled voltages increased from 0.49V to 0.65V under a no-load condition. With load capacitors of 10pF and 20pF, the ranges of the oscillating frequency became 150kHz ∼ 3MHz and 140kHz ∼ 2MHz, respectively. The circuit consumes 280 μm× 150 μm chip area and dissipates 16.8 μw. |
本系統中英文摘要資訊取自各篇刊載內容。