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題名 | Simulation of VLSI Lossy Interconnects with Nonlinear Terminals=超大型積體電路非線性終端之損失連接線模擬 |
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作 者 | 詹耀福; 楊明豐; | 書刊名 | 大同學報 |
卷期 | 25 1995.11[民84.11] |
頁次 | 頁155-169+435 |
分類號 | 448.57 |
關鍵詞 | 積體電路; 連接線; |
語文 | 英文(English) |
中文摘要 | 由於積體電路技術的進步,使元件交換時間降低,但是元件之間連接線的電氣性 能並未隨著提高,因此在高速積體電路的設計和分析上,連接線的電氣暫態特性分析變得更 加重要。本論文提出一個以修正節點分析導納矩陣為基礎的方法,把一般網路公式化,其包 含損失耦合傳輸線、非線性元件和連接線網路,我們使用分段線性方法發展出非線性元件等 效電路模型。經由模擬,我們證明所發展的程式其速度比 SPICE 更快,與 SPICE 的執行結 果比較, 對一般非線性網路而言,模擬誤差在 5 %之內,而含傳輸線網路其誤差也維持在 10 %之內。 |
英文摘要 | The recent advance of integrated circuit technology has reduced the single device switching time. Unfortunately, the electrical performance of intereonnections between devices does not scale as well. Therefore, the evaluation of electrical transient performance of interconnection lines is becoming increasingly important in the design and analysis of high-speed integrated circuits. In this paper, a method based on the modified nodal admittance (MNA) matrix is presented for the formulation of the network equation including the coupled lossy transmission lines, nonlinear components, and interconnecting networks. We develop an analytic expression for the equivalent resistance model of an inverter by using a piecewise linear (PWL) method. The simulation speed of the experimental simulator is proved faster than SPICE. The simulation error is within 5 percent for network without transmission lines and 10 percent for interconnect network when compared with SPICE results. |
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