查詢結果分析
相關文獻
- 精確類比電路設計之非匹配特性研究
- 次微米互補型金氧半場效電晶體匹配特性與製程因子的研究
- 以類比電路設計Head Phone
- Current-mode Universal Biquad Using Differential Difference Current Conveyors and Current Followers
- Generalized Active Immittance Simulator Using Differential Voltage Current Conveyors
- 以類比電路設計Head Phone
- Generalized-Impedance Converter Using Differential Voltage Current Conveyors
- Realization of Voltage-mode Single-resistance-controlled Sinusoidal Oscillator Using Commercially Available Integrated Circuits
- Grounded-inductor Employing Differential-voltage Current Conveyors
- Novel Realization Filter Employing Single Differential Voltage Current Conveyor
頁籤選單縮合
題 名 | 精確類比電路設計之非匹配特性研究 |
---|---|
作 者 | 王是琦; 劉紹宗; | 書刊名 | 逢甲學報 |
卷 期 | 28 1995.11[民84.11] |
頁 次 | 頁437-443 |
分類號 | 448.532 |
關鍵詞 | 類比電路設計; 非匹配特性; |
語 文 | 中文(Chinese) |
中文摘要 | 本篇論文旨在討論用 0.5 微米互補型金氧半場效電晶體之製程技術來研究精確類 比電路之非匹配特性。藉由一個新的金氧半場效電晶體模型,我們發展出一套有系統的法則 來淬取非匹配參數。再者,我們也研究了佈局、元件大小、和偏壓對非匹配特性的影響。這 套淬取非匹配參數的法則,可用在通道長度小於 0.5 微米之金氧半場效電晶體。 本論文提 供了一個完整的法則,來模擬類比電路之非匹配特性。 |
英文摘要 | This paper studies the mismatch characteristics in a 0.5 μm CMOS technology for precision analog design. Based on a novel MOSFET's model, a systematic algorithm is developed to extract the mismatch parameters. Moreover, the dependence of mismatch characteristics on layout, device size, and bias are also evaluated. The extraction method is proved to be good for channel length down to 0.5 μ m. This paper provides a complete algorithm for modeling the mismatch characteristics in analog circuit design. |
本系統中英文摘要資訊取自各篇刊載內容。