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題 名 | CAD Automatic Design of Multilevel NAND Gate Networks Using Permissible Cubes and PCRM Graph=多階層反及閘邏輯網路之合成及用PCRM 圖之電腦輔助設計方法 |
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作 者 | 陳兩嘉; 涂宏泰; | 書刊名 | 中原學報 |
卷 期 | 22 1993.12[民82.12] |
頁 次 | 頁98-112 |
分類號 | 448.6 |
關鍵詞 | 零壹交替法; 容許方體全及項關係圖; 容許方體; Permissible-cube- related-minterm graph; Permissible cube; Zero-one-interaction; |
語 文 | 英文(English) |
中文摘要 | 本論文是設計一計算機輔助系統,以快速設計多階層反及閘(NANDgate)邏輯網路。輸入任一數位函數,利用吾人所發展之計算機輔助軟體工具,可快速設計出所需之多階層反及閘邏輯網路。本軟體工兵並具有網路化簡、階層化簡及閘數化簡功能。設計方法係利用零壹交替法(Zero-OneInteraction)及容許方體全及項關係圖(Permissible-Cube-Related-Minterm graph) ,以尋取設計所需各階層網路之容許方體(Permissible cube) ,建立各反及閘之輸入變數。在電腦輔助設計中,利用容許方體全及項關係圖建立獨特之資料結構,以自動尋取容許方體。本軟體工具可接受任何數目之輸入非補數變數(Uncomplemented variables) ,並快速設計出幾近最簡之多階層反及閘邏輯網路。 |
英文摘要 | A computer-aided design procedure for the automatic design of multilevel NAND gate logic networks as encountered in the synthesis of VLSI logic circuits is presented in this paper. A very powerful technique using logic Zero-One-Interaction of permissible cubes is among the salient features in our developed synthesizing algorithm for NAND gate logic network. Only uncomplemented inputs are involved in this automatic NAND gate network design technique. Hence, less NAND gates are required in the synthesized logic network. The developed algorithm for the automatic design of NAND gate logic networks is feasible for any number of input variables. The algorithm is implemented in C language using software approach of our developed powerful data structure, Permissible-Cube-Related-Minterm (PCRM) graph, to generate automatically the set of required permissible cubes. The automatic level-reduction and gate-reduction of logic network using software CAD approrch is also given in this paper. The algorithms in this paper provide the CAD automatic synthesis of nearly minimal multilevel NAND gate logic network. |
本系統中英文摘要資訊取自各篇刊載內容。