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題 名 | Hardware Support for Multiprocessor Systems to Handle Branches and loops=多處理機系統處理分支及迴路的硬體支援 |
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作 者 | 謝忠健; 陳慧如; | 書刊名 | 大同學報 |
卷 期 | 22 1992.11[民81.11] |
頁 次 | 頁253-260 |
分類號 | 448.595 |
關鍵詞 | 分支; 多處理機; 系統; 迴路; 處理; 硬體; |
語 文 | 英文(English) |
中文摘要 | 在本篇論文中,我們提出一種協助解決多處理機系統中處理分支及迴路的機構。 系統中的每個處理單元都加入一個狀態暫存器( status register )來紀錄每個分支在執 行時所走的路徑。 而相對於此狀態暫存器的每一個位元, 都有一個計數暫存器( counter register )與其對應來處理迴路之同步化。 我們所使用的模擬程式為 AHPL (硬體描述語 言)的 HPSIM 軟體。經實驗求得寫的動作可在兩個時脈,讀可在三個時脈完成。 本機構被 運用於時隙預留細微排序法則中,結果令人滿意。 |
英文摘要 | A status recording mechanism is designed and implemented to handle the branches and loops within application programs which are going to run on a multiprocessor system. This mechanism includes a ready register, a status register and a counter register. A branch/loop is assigned an ID number during program analysis and allocated a bit in each of the three registers. By properly use of this mechanism, the application programs can be scheduled for multiprocessor system. The operation of this mechanism, as designed and simulated by AHPL and HPSIM respectively, can be finished within 2 clocks for read and 3 clocks for write. |
本系統中英文摘要資訊取自各篇刊載內容。