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題名 | Built-in self testing for complex digital integrated circuits=數位積體電路內建自測線路之研究 |
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作者 | 童萬福; | 書刊名 | 中華工專學報 |
卷期 | 6 1991.01[民80.01] |
頁次 | 頁207-222 |
分類號 | 448.57 |
關鍵詞 | 自測線路; 研究; 數位; 積體電路; |
語文 | 英文(English) |
中文摘要 | 在傳統上,所有試驗數位電路的理論與方法,例如D演算法,PODEM演算法及Level Sensitive Scan Design等均需要外加大量的測試模式。而相反的,受測線路本身內部能提 供的測試點數量由於積體電路體積愈來愈小的趨勢下受到了限制,而當數位系統的複雜度愈 形提高之下,也就形成了不易測試的瓶頸。 本文即在討論一種不需要任何外加測試模式或設備,而由線路自行產生最少的測試模式,由 測試結果之數據來判斷內部線路的故障所在位置,此即稱為內建自測線路(Built-in Self Test),並利用平行信號分析法(Parallel Signature Analysis)證明了內建自測線路的 可靠性。假亂數測試模式產生器(Pseudorandom Test Pattern Generater)以及線性回授 移位暫存器(Linear Feedback Shift Register)被使用來測試史奈特電路,檢測出線路上 的0,1值本應隨機而變而卻發生永遠為0或永遠為1的Stuck-at-fault。 |
英文摘要 | The development of computers has been stimulated greatly by IC technology. Circuit density has increased dramatically. With these developments, reliability has become more important. However, the Conventional testing philosophies, such as D Algorithm, PODEM Algorithm and Level-Sensitive Scan Design, are all based externally applied test patterns. A primary weakness of those methods is that all extremely constrained by limited access to internal point in the Circuit under test. When the digital systems grow more complex and more difficult to test, it becomes increasing attractive to Built-in Self Testing (BIST) in which test patterns are applied internally to the Circuit under test (CUT) without the using of external test equipment. The feasibility of using parallel signature analysis for Built-in self test prupose is demonstrated by a Schneider circuit. Pseudorandom test pattern generater (PTPG) with Linerar feedback shift Registers (LFSR) are successfully used for detecting stuck-at-fault of a Schneider circuit. |
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