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題名 | 三維積體電路直通矽穿孔技術之應用趨勢與製程簡介=Application Trend and Fabrication Introduction of 3D Integrated Circuits through Silicon Vias Technology |
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作者 | 劉建惟; | 書刊名 | 奈米通訊 |
卷期 | 20:3 2013.09[民102.09] |
頁次 | 頁20-27 |
分類號 | 448.57 |
關鍵詞 | 三維積體電路直通矽穿孔; 應用趨勢; 製程簡介; 先鑽孔; 中段鑽孔; 後鑽孔; 接合後鑽孔; 3D integrated circuits through silicon vias; 3D IC TSV; Application trend; Fabrication introduction; Vias-first; Vias-middle; Vias-last; Vias after bonding; |
語文 | 中文(Chinese) |
中文摘要 | 三維積體電路直通矽穿孔技術是一項延續摩爾定律的有效解決方案。具有直通矽穿孔、薄化晶圓、以及矽對矽細微間隙內連線之主動元件的三維矽封裝整合提供了許多產品優勢。三維積體電路直通矽穿孔技術的優點包括有:多功能異質整合、功率損耗減少、產品微型化、元件性能提升、成本降低、及產品即時上市等。在本文中,針對三維積體電路直通矽穿孔技術的應用趨勢及所謂的先鑽孔、中段鑽孔、後鑽孔與接合後鑽孔等直通矽穿孔技術之製程簡介將會為讀者做詳細地說明。 |
英文摘要 | The three-dimensional integrated circuits through silicon vias (3D IC TSV) technology is a powerful solution for continuing the Moore’s law. The 3D silicon packaging integration of active devices with TSV, thinned silicon wafer, and silicon to silicon fine-pitch interconnections offers many product benefits. The advantages of 3D IC TSV technologies can include the following: multi-functions hetero-integration, power consumption reduction, product miniaturization, device performance enhancements, cost reduction and product for time to market. In this paper, the application trend of 3D IC TSV technology and fabrication introduction of so-called vias-first TSV, vias-middle TSV, vias-last TSV and vias after bonding TSV technologies will be described in detail for readers. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。