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題 名 | A Detailed Placement and Legalization Method for Placement Finishing=元件細部擺置與合理化問題之解決方法 |
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作 者 | 鄭維凱; 邱彥衡; 邱奕瑄; 徐永豪; | 書刊名 | 先進工程學刊 |
卷 期 | 10:2 2015.04[民104.04] |
頁 次 | 頁57-66 |
分類號 | 448.57 |
關鍵詞 | 實體合成; 元件擺置; 連線半周長; 元件擺放密度; 可繞線度; Physical design; Detailed placement; Half-perimeter wirelength; HPWL; Placement density; Routability; |
語 文 | 英文(English) |
中文摘要 | 元件擺置是積體電路設計流程中,實體合成步驟最重要的工作之一。在此階段,我們決定每個元件在電路中的擺放位置,除了設計規則的合理化問題外,並且盡可能減少元件之間的連線長度與增加繞線工作完成的可行性。在此論文中,我們提出了一個解決此問題的演算法,包括最佳區域位移、垂直方向交換、水平順序重置、元件群組等步驟。除此之外,我們並提出一個評估元件擺放位置的效益函式,以引導前述步驟的進行。實驗結果顯示,我們所提出的演算法與效益函式在加權後之連線半周長與元件擺放密度的綜合評估上,可以得到有效的改善。 |
英文摘要 | Placement is one of the most important physical design stages in the VLSI design flow. This step determines the locations of cell elements to get better circuit design in terms of wirelength and routability. In this paper, we propose a detailed placement and legalization algorithm under the maximum displacement constraint after the global placement stage. The flow of our algorithm includes optimal region movement, vertical swapping, reordering, and clustering. A benefit function is proposed to take into account both the wirelength and routability issues, and guide the process of each step in the algorithm. In comparison with the benefit function that considers the wirelength issue only, experimental results show that our benefit function can reduce a great deal of placement density with only a little increase in wirelength, and gets better results in terms of scaled HPWL which is composed of the half-perimeter wirelength (HPWL) and the weighted placement density issues. |
本系統中英文摘要資訊取自各篇刊載內容。