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題 名 | 新型低功率雙邊緣觸發正反器設計=A Novel Low-Power Dual Edge-Triggered Flip-Flop Design |
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作 者 | 余建政; 陳冠廷; | 書刊名 | 修平學報 |
卷 期 | 24 2012.03[民101.03] |
頁 次 | 頁59-68 |
分類號 | 448.532 |
關鍵詞 | 低功率; 雙邊緣觸發正反器; 資料傳輸率; Low-power; Dual edge-triggered flip-flop; Data rate; |
語 文 | 中文(Chinese) |
中文摘要 | 在相同的時脈頻率下,雙邊緣觸發正反器能夠提供兩倍於單邊緣觸發正反器的資料傳輸率。在低功率 VLSI電路設計中,雙邊緣觸發正反器的使用已廣泛的受到重視。本文提出一種新型低功率雙邊緣觸發正反器電路設計,並與四篇先前之雙邊緣觸發正反器電路,在不同工作電壓和不同工作頻率下,針對功率損耗和功率延遲乘積(Power-Delay Product; PDP)加以分析比較。 本論文係使用 TSMC 180nm的製程技術模擬。根據模擬結果顯示,本論文所提出之雙邊緣觸發正反器能有效減少功率損耗達 53.8%,並能改善功率延遲乘積達 70%。 |
英文摘要 | The dual edge-triggered flip-flops (DETFFs) use both clock edges and can provide a data rate that is twice that of single edge-triggered flip-flops for the same clock frequency. In the research of low-power VLSI circuits design, the use of DETFF has gained more attention. In this paper, we present a novel low-power DETFF design and compare four previously published DETFFs with our proposed design for their power dissipation and power-delay product (PDP), at different voltage and frequency. HSPICE simulation results employing TSMC 180nm CMOS technology indicate the proposed flip-flop can reduce effectively power dissipation up to 53.8% as compared to other DETFFs. Moreover, the improvement in power-delay product is enhanced up to 70%. |
本系統中英文摘要資訊取自各篇刊載內容。