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題 名 | Large-scale Circuit Simulation for MOSFET Circuits with Interconnects Using Iterated Timing Analysis and Latency-checking Method=使用ITA 演算法和休眠檢測模擬MOSFET 加上連接線之大型電路 |
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作 者 | 陳俊榮; 蔡昌隆; 孫振東; 李志仁; 張耀鴻; 周立平; 楊泰寧; | 書刊名 | 華岡工程學報 |
卷 期 | 27 2011.01[民100.01] |
頁 次 | 頁125-131 |
分類號 | 448.532 |
關鍵詞 | 電路模擬; 傳輸線; 基於鬆弛; ITA演算法; 休眠; Circuit simulation; Transmission lines; Relaxation-based; ITA algorithm; Latency; |
語 文 | 英文(English) |