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題 名 | 適用於NG-PON的突發式時脈與資料回復電路的設計策略與實作=The Design Concept and Implementation of Burst-Mode Clock and Data Recovery Circuits for NG-PON |
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作 者 | 林榮茂; | 書刊名 | 電腦與通訊 |
卷 期 | 135 2010.10[民99.10] |
頁 次 | 頁11-17 |
專 輯 | 多重服務網路接取技術專題 |
分類號 | 448.6 |
關鍵詞 | 被動光纖網路; 突發式時脈與資料回復電路; Passive optical network; Burst-mode clock and data recovery circuit; BMCDR; PON; |
語 文 | 中文(Chinese) |
中文摘要 | 目前許多國家在光纖到府(Fiber To The Home; FTTH)的推動上已經大量的普及,使得下一代被動光纖網路(Next Generation Passive Optical Network; NG-PON)架構格外受到矚目。在PON的架構中,光纖線路終端機(Optical Line Terminal; OLT)的前端接收器中需要一個鎖定時間規格非常嚴格的突發式時脈與資料回復(Burst-Mode Clock and Data Recovery; BMCDR)電路。在本篇文章中,將從PON在前端接收器的規格需求中,介紹各式可工作於突發式時脈與資料回復電路之架構,並分析其工作狀態與電路特色,最後並提出一個2.5Gbps具有相位校正功能的過取樣BMCDR電路,此電路可以於31bits的資料時間內快速決定資料相位區間並輸出回復的資料。 |
英文摘要 | Recently, the Fiber To The Home (FTTH) has been dramatically deployed in many countries. The Next Generation Passive Optical Network (NG-PON) architecture has been attracted researcher's attentions as well. In the PON architecture, the front-end receiver of the Optical Line Terminal (OLT) must include a Burst-Mode clock and Data Recovery (BMCDR) circuit, which requires a very strict lock time specification for recovering the input data. In this paper, we introduced several architectures of BMCDR circuit to conform the specification of the PON front-end receiver. Then, we also analyzed the operation and characteristic of these circuits. Finally, we proposed a 2.5Gbps BMCDR circuit based on oversampling technique which provided the ability of phase error cancellation. This circuit could decide the data phase interval and output the recovery data quickly in 31bits data time. |
本系統中英文摘要資訊取自各篇刊載內容。