查詢結果分析
相關文獻
- 於FPGA平臺製作具有疊代停止之渦輪解碼器
- The Calculation of Complexity in Normal and Apoplectic EEG Signals
- Measurements for Rule Based Systems
- Parallel Two-dimensional Prefix Computation on a Mesh-connected Computer
- 動態批量平行演算法之探討
- Effects of Task Complexity on Reaching Kinematics: A Pilot Study
- 資優兒童問題解決能力實作評量之建構研究
- 改進CELP隨機碼本的搜尋方法之研究
- 行動或狀態導向、目標層次、工作複雜度對國中生行動控制策略與工作表現之影響
- 造形複雜度之探討
頁籤選單縮合
題 名 | 於FPGA平臺製作具有疊代停止之渦輪解碼器=Implementation of a Turbo Decoder with Iteration Stopping by FPGA Platform |
---|---|
作 者 | 黃樹林; 張創然; 周泰祥; | 書刊名 | 明志學報 |
卷 期 | 40:1 2008.06[民97.06] |
頁 次 | 頁91-99 |
分類號 | 448.532 |
關鍵詞 | 渦輪碼; 疊代停止機制; 複雜度; Turbo code; Iteration stopping rules; Complexity; |
語 文 | 中文(Chinese) |
中文摘要 | 渦輪碼(Turbo code)通道編碼機制提供一個接近通道容量的編解碼實作技術。由於渦輪編解碼於傳遞訊息方面的優異性,適用在第三代通訊(3G)的應用上。因其電路複雜度過高,使其無法輕易應用到無線行動系統上。降低電路複雜度對現今的渦輪碼來說是一個相當重要的研究課題,因此本文以SW-Log-MAP(slide window-logarithm-maximum a posteriori)架構於FPGA上實現渦輪解碼器並探討加入疊代停止機制所能降低的複雜度。使用Cyclone Ⅱ家族EP2C70F896晶片建構渦輪解碼器,合成後其 t d 為29.958ns 而 f mas 為13.51 MHZ。由軟體驗證分析顯示,於固定點模型疊代停止設計中,硬式規則與傳統固定疊代次數相比,大於1db 以上明顯可減少約平均70%以上之疊代次數,可有效降低運算複雜度與時間。 |
英文摘要 | The channel coding using turbo code is close to the capacity of channel in 3G applications. However, the circuit is complexity, we can not easy to use for wireless communication systems. Reducing the circuit complexity of turbo decoder is very important. The architecture of decoder has been implemented with structural SW-Log-MAP(slide window-logarithm-maximum a posteriori) by FPGA and uses the iteration stopping rules to reduce circuit complexity in this thesis. Our decoder has been verified in hardware with Altera Cyclone Ⅱ Family EP2C70F896C6 Device, and t d is 29.958ns and f mas is 13.51 MHz. Simulation results show that the proposed architecture reduces average numer of iterations about 70% comparing with the other turbo coders used a fixed number of iterations for signal noise rate over 1.3 db. |
本系統中英文摘要資訊取自各篇刊載內容。