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題 名 | 利用VHDL設計乘法器=Implement of Multiplier by Using VHDL |
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作 者 | 許地申; | 書刊名 | 中華技術學院學報 |
卷 期 | 29 2003.12[民92.12] |
頁 次 | 頁1-17 |
分類號 | 448.595 |
關鍵詞 | 非常高速積體電路硬體描述語言; 電路描述; 電路合成; 電路模擬; VHDL; Circuit description; Circuit synthesis; Circuit simulation; |
語 文 | 中文(Chinese) |
中文摘要 | 在計算機結構裡加,減,乘、除是常被用到的運算,本文提出以非常高速積體電路硬體描述語言(VHDL)來描述硬體,說明如何將兩個運算元作相乘的運算。我們首先以無路數整數做乘法運算來說明其原理,設計其電路結構。其實在VHDL程式中,我們更可以載入STD_LOGIC_ARITH與STD_LOGIC_UNSIGNED元件盒之後,直接進行乘法運算,既簡單又容易擴充。最後,我們將以4-bit X 4-bit 的例子來做電路描述、電路合成、電路模擬並以七段顯示器將其結果顯示出來。 |
英文摘要 | We have known operation that perform addition, subtraction, multiplication, and division. In this paper we are presented primarily to describe hardware using by VHDL. We can explain how multiplication may be performed for two operand. Multiplication of unsigned numbers illustrates the main issues involved in the design of multiplier circuit. In fact, after the STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED packages were added to the VHDL program, it became not only simple but also easy to extended. Next, consider a 4×4 example to circuit description, circuit synthesis, and circuit simulation by using VHDL. Finally, this approach can also be displayed by 7-segment. |
本系統中英文摘要資訊取自各篇刊載內容。