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題名 | IS-95劃碼多重進接之碼擷取硬體設計=IS-95 CDMA Code Acquisition Hardware Design |
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作者 | 李俊逸; 周士鈞; 謝素琴; | 書刊名 | 電信研究 |
卷期 | 32:4 2002.08[民91.08] |
頁次 | 頁439-453 |
分類號 | 448.84 |
關鍵詞 | 劃碼多重進接; 碼擷取; 場可程式閘陣列; CDMA; Code acquisition; FPGA; |
語文 | 中文(Chinese) |
中文摘要 | 全球無線通訊市場在最近幾年呈現爆炸性的成長,因而使得無線通訊相關技術研究成為目前非常熱門的領域。第三代無線通訊技術,不論是WCDMA或是CDMA2000,都以CDMA展頻與解展頻技術作為核心。展頻碼擷取技術在IS-95 CDMA接收機的同步與解展頻架構中扮演著舉足輕重的角色。本文中除了說明碼擷取模組設計的原理外,並利用Verilog RTL連結FPGA程式庫來進行硬體電路之模擬與驗證。 |
英文摘要 | As the worldwide wireless communication market is experiencing an explosive growth in the recent years, the wireless communication and the other related technologies have become the most popular research fields. The third generation, 3G wireless communication technologies, namely WCDMA and CDMA2000, are all based on the core in CDMA spreading and de-spreading technologies. Code acquisition plays a very significant role of the architecture of code synchronization and code dispreading of a CDMA direct-sequence spread-spectrum receiver. In this paper, the theory and design of a code acquisition module for a IS-95 CDMA spread-spectrum receiver will be described. To verify the theory, the module hardware design is verified via Verilog HDL simulation using a FPGA library. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。