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題 名 | 嵌入式快閃記憶體性能之改善=Performance Improvement of Embedded Flash Memory |
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作 者 | 黃恆盛; 黃嘉宏; 莊棓仰; | 書刊名 | 臺北科技大學學報 |
卷 期 | 35:1 2002.03[民91.03] |
頁 次 | 頁9-16 |
分類號 | 471.6511 |
關鍵詞 | 嵌入式快閃記憶體; 低功率; 淺溝槽絕緣; 可靠度衰退; 耦合率; Embedded flash memory; Low power; Shallow trench isolation; STI; Reliability degradation; Coupling ratio; |
語 文 | 中文(Chinese) |
中文摘要 | 在現今嵌入式淺溝槽快閃記憶體中,符合未來性能要求之寫入/擦拭耦合率的設計已經被提出討論。探討此項的原因是在現今低功率快閃元件中大都使用淺溝槽道絕緣(Shallow Trench Isolation, STI)技術,如此會引發嚴重的施加應力而導致可靠度劣化(Stress Induced Reliability Degradation) SIRD問題。在本文中,我們提出一種汲極(或源極)側的擦拭方法以應用在低電壓操作和快速資料寫入上。另外,元件也必須操作在適當工作偏壓下以達到最佳可靠度。未來在控制可靠度均勻性的改善方面,我們提出一種修正型STI絕緣技術模組和元件汲極側工程兩種技術,並使用256K NOR-type內嵌式低功率快閃元件加以驗證。 |
英文摘要 | The design of programming/erasing (P/E) coupling rations of advanced low-power embedded flash cells (working as an on/off switch) with a shallow trench isolation (STI) structure has been discussed to meet future performance requirement. The reason that the stress-induced reliability degradation (SIRD) problem becomes more severe when the STI structure is used in a low-power flash cell has also been explained. In this paper, we suggest a drain (or source) side erase method for both lower-voltage operation and quick data writing. This device must be operated at a suitable bias condition to achieve the best reliability. For further improvement in the control and uniformity of the reliability performance, a modified STI module and modified cell drain side engineering are proposed and verified on a 256K NOR-type embedded low-power flash test vehicle. |
本系統中英文摘要資訊取自各篇刊載內容。