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題名 | 近年來另類乘法器的研究=The Development for Another Multipliers in Recently Years |
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作者姓名(中文) | 莊作彬; | 書刊名 | 大仁學報 |
卷期 | 21 2001.12[民90.12] |
頁次 | 頁35-45 |
分類號 | 310.153 |
關鍵詞 | 計算機算術; 乘法運算; 超大型積體電路設計; Computer arithmetic; Multiplication; VLSI Design; |
語文 | 中文(Chinese) |
中文摘要 | 乘法運算是數位信號處理中最主要的運算之一,它同時也是佔了最多時間及消耗功率的元件。過去有關乘法器的研究論文相當廣泛,但是都集中在平行乘法器設計架構上作一些改良,近年來有兩項非常重要的另類乘法器興起,分別是捨棄式乘法器及以及排序網路為基礎之乘法器。本論文先介紹基本乘法器的原理,再深入探討這兩類的乘法器的工作原理,並且提出了未來的之研究方向。 |
英文摘要 | Multiplication is one of the mainly used operations in digital signal processing. It is time and power consuming. In the past there are many research papers proposed about multiplier design, but they only concentrate on the parallel multipliers. In recent years there are two important other multipliers proposed in some important papers. In this paper the author will introduce the basic concept of a multiplier, and give a thoroughly review of these two multipliers-one is called truncated multiplier and the other is called sorting network based multiplier. Also the author points out future research directions. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。