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頁籤選單縮合
題 名 | Wide Address Translation and Protection for Single Address Space Operating Systems=單一位址空間作業系統下高位元虛擬位址轉換與保護 |
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作 者 | 謝續平; 徐英傑; 沈長毅; | 書刊名 | Proceedings of the National Science Council : Part A, Physical Science and Engineering |
卷 期 | 22:5 1998.09[民87.09] |
頁 次 | 頁616-626 |
分類號 | 312.1 |
關鍵詞 | 單一位址空間作業系統; 位址轉換; 位址保護; Wide address; Single address space operating systems; Virtual memory simulator; |
語 文 | 英文(English) |
中文摘要 | 傳統的虛擬記憶體管理多被用於像UNIX一樣的私有虛擬空間的作業系統,但並 不能有效地應用於單一位址空間作業系統。在這篇論文中,我們提出一個新的虛擬記憶體保 護模組來管理單一位址空間。藉著將64位元的虛擬位址空間分成2□個2□位元的區段,作 業系統必須管理關於每個行程的區段表以及每區段的位址轉換表。每個區段表上記錄這個行 程可存取的區段以及區段的位址轉換表的位置,藉著將區段表暫存在我們所提出的一個新快 取記憶體架構上,位址之轉換及存取權限之檢查的時間都會縮短。而且藉由分開的位址轉換 及位址保護快取架構,傳統耗費在行程轉換所作的虛工也大量被減少。在我們的模擬結果中 顯示,這個虛擬記憶體管理架構的確增加了在單一位址空間作業系統中虛擬記憶體轉換及保 護的效能。 |
英文摘要 | In this paper, we present a new address translation and memory protection model to manage the wide 64-bit virtual address space, called the segment-based translation and protection (SBTP) model. It partitions a 64-bit virtual address space into 2□ segments with equal size of 2□ bytes. The SBTP model maintains a segment table to record used segments for each process. As a result of caching the per-process basis segment table on a designed memory cache, called the segment look-aside buffer (SLB), the virtual address translation time and protection rights verification time can be reduced. Furthermore, by separating the hardware mechanisms of address translation and protection, mapping information stored in the translation look-aside buffer (TLB) can be shared by all the processes and need not be flushed on each context switch. Thus, the cost of context switching compared with that conventional architectures is greatly reduced. Simulation results show that the proposed memory architecture effectively improves the performance of wide virtual address translation and memory protection for single address space operating system. |
本系統中英文摘要資訊取自各篇刊載內容。