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題 名 | Waveform Approximation Technique for CMOS Gates in the Switch-Level Timing Simulator Bts=開關階層時序模擬器BTS之波形近似技術 |
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作 者 | 張茂林; 王志恆; 易序忠; 馮武雄; | 書刊名 | 中國工程學刊 |
卷 期 | 21:3 1998.05[民87.05] |
頁 次 | 頁255-268 |
分類號 | 448.595 |
關鍵詞 | 時序模擬; 波形近似技術; RC樹; Waveform approximation technique; Switch-level timing simulation; RC tree; |
語 文 | 英文(English) |
中文摘要 | 開關階層時序模擬器有快速與適用於VLSI電路的優點,但是卻無法提供 精確的波形資訊。本文提出一準確且效率的開關階層時序模擬器。高準確性 係源自一新的波形近似技術,此技術包含延遲評估與斜率評估。有效率的延遲 與斜率之計算則是以開關階層模擬取代電晶體階層模擬而達成。延遲評估的新 方法將在文中描述:此法以二個方程式來模型化RC樹的延遲行為,而此二式 分別稱之為主要延遲方程式與誤差延遲方程式。二者皆以曲面擬合(surface fitting)去近似量自CMOS閘之實際延遲行為所產生之曲面。另外,斜率評估 的方法也作了進一步的修改。斜率與電路之等效RC時間常數有著密切的關 係。而等效RC時間常數可以經由經RC樹作遞迴式的拜訪而獲得。模擬結果 與SPICE比較,有令人滿意的結果。 |
英文摘要 | A Switch-level timing simulator has the advantage of fast speed and good adaptability for VLSI circuits, but it cannot offer accurate transient waveform information. In this paper an accurate and efficient switch-level timing simulator is described. The high accuracy is attributed to a new waveform approximation technique, which includes delay estimation and slope estimation. Efficient delay and slope calculations are accomplished throuhg a switch-levle simulation instead of using a transistor-level simulation. A new approach for delay estimation is presented which models the delay behavior of an RC tree by two equations; a dominant delay equation and an error delay equation. Both are derived by surface fitting to approximate the surface that is measured from the actual delay behavior of a CMOS gate. A modified approach for slope estimation is also investigated which has close relationship with the equivalent RC time constant of the evaluated cluster circuit. This equivalent RC time constant can be obtained by traversing the tree recursively. The results show good agreement with SPICE. |
本系統中英文摘要資訊取自各篇刊載內容。