頁籤選單縮合
題 名 | High-Speed Two-Dimensional OEIC Transceiver Arrays=高速二次元光電陣列積體電路 |
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作 者 | 張維恆; 馮明; | 書刊名 | Journal of the Chinese Institute of Electrical Engineering |
卷 期 | 4:3 1997.08[民86.08] |
頁 次 | 頁213-225 |
分類號 | 448.552 |
關鍵詞 | 光電積體電路; 二次元陣列; 金屬半導體場效電晶體; Two-dimensional arrays; Smart-pixel; OEIC; Transimpedance amplifier and MESFET; |
語 文 | 英文(English) |
英文摘要 | 基於對未來高速電腦資料傳輸之需求,我們設計了高速二次元陣列。此種陣列最高 可傳送及接收可傳送及接收快於每秒六百四十億位元之資料。相對於其他使用異質接面偶極 電晶體或高電子遷移率場效電晶體類高製造雜度之元件,便於製造之離子佈值�d化鎵金屬半 導體場效電晶體及金半金光電二極體被用為主要之元件。如此之組合可用於生產低價高速之 光電積體電路。 此種二次元 4 × 4 或 8 × 8 陣列使用 Vitesse 公司之 HGaAs- Ⅲ 0.6 μ m 金屬半導體場效電晶體製程。 設計之目標為每秒一百六十及六百四十億位元,消耗少 於一百 mW/channel 及低於負二十 dBm 之感度。 電路為完全直流偶合,以便保持資料之完 整性。 4 × 4 或 8 × 8 陣列使用了各約五千及二萬元件,電腦模擬之結果顯示此積體電 路達成了低耗電率、高速、高密度、高感度、高製程及電源變化容忍度之設計目標。 make this technology favorable in realizing low-cost, high-perofrmance OEICs (Opto-Electronic Integrated Circuits).Two-dimensional 4 × 4 and 8 × 8 smart-pixel arrays utilizing Vitesseis HGaAs- Ⅲ 0.6 μ m E/D MESFET process have been developed. The main design goals are aggregated data rates of 16 and 64 Gb/s (at Gb/s/channel for 4 × 4 and 8 × 8 arrays), power consumption less than 100 m W/channel, and sensitivity of better than -20 dBM. To make the data transmission transparent, fully dc-coupled circuits are designed. Obstacles in array implementation are also overcome, by the novel design of the fully differential optical receivers. Approximately 5,000 and 20,000 active devices are integrated in the 4 × 4 and 8 8 arrays, respectively. The simulated results of the complete circuits show that the design goals of low power, high speed, high density,high sensitivity, process and power supply tolerance are met. |
本系統中英文摘要資訊取自各篇刊載內容。