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題 名 | 設計和製作一高度公平性之匯流排仲裁晶片=Design and Implementation of a High-Fair Bus Arbitration Chip |
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作 者 | 李炯三; | 書刊名 | 技術學刊 |
卷 期 | 12:3 1997.09[民86.09] |
頁 次 | 頁439-444 |
分類號 | 448.595 |
關鍵詞 | 仲裁規約; 晶片; 公平性之匯流排仲裁器; 多重處理機系統; Arbitration protocol; Chip; Fair bus arbiter; Multiprocessor system; |
語 文 | 中文(Chinese) |
中文摘要 | 本篇論文發表一顆"具公平性之匯流排仲裁晶片"的電路架構及相關的仲裁規約 。該仲裁晶片可用在共匯流排多重處理機系統上,確保每個CPU均能使用到匯流排,使每 個CPU均有近似相等的匯流排使用率及匯流排等待時間。這個仲裁器是根據一個改良型的 群體仲裁規約所設計出來的。 |
英文摘要 | This paper proposes the circuit structure of a high-fair bus arbitration chip which can be used in a shared-bus multiprocessor system to maintain bus fairness. The chip not only guarantees that the processor with the lowest priority will gain access to the bus without being completely locked out, as might happen during heavy traffic, but also assures that both the bus waiting time and utilization on average of each processor are approximately equal to each other. The chip to be designed and implemented is based on a new bus arbitration protocol which is modified according to the group arbitration protocol. |
本系統中英文摘要資訊取自各篇刊載內容。