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題名 | VLSI Chip Design of Viterbi Decoder with Reduced-state Algorithm=一種減少狀態點數魏特比解碼器之超大型積體電路晶片設計 |
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作者姓名(中文) | 李文達; | 書刊名 | 臺北技術學院學報 |
卷期 | 28:1 1995.03[民84.03] |
頁次 | 頁197-210 |
分類號 | 448.57 |
關鍵詞 | 魏特比解碼器; 減少狀態點數演算法; 結構化矽編譯器; Viterbi decoder; Reduced-state algorithm; Structural silicon compiler; |
語文 | 英文(English) |
中文摘要 | 本論文中,作者提出一種減少狀態點數之魏特比解碼法,本法是使用 一設限值於每級運算�塈@動態之判斷,可以事先將較不可能之點數予以捨去,而 只保留較為可能之狀態點數。這和傳統的魏特比解碼法比較,可以有效減少運算 量,進而加快解碼之速度。本文也藉由結構化矽編譯器之輔助,提出以階層化、 模組化魏特比解碼器之超大型積體電路架構設計。此一解碼器之記憶級數為7, 面積為 9.5x8.5mm共使用了45214個電晶體,而該一解碼器適用於中等速度之通 訊系統中。 |
英文摘要 | In this paper, we present a chip design of Viterbi decoder withreduced-state algorithm. This algorithm is realized by checking thresholdstrategy adapdvely in each stage. The survivor states from the unlikelihoodwill be ignored, and the state number of each stage to be computed isreduced significantly in comparision with conventional Viterbi decoder andhence the decoding speed is increased. Hierarchical and modular techniquesare used to design the reduced-state Viterbi decoder with the aid ofstructural silicon compiler. The single-chip decoder with constraint lengthk=7 has been designed in 1.2 mm CMOS technology. The chip area is 9.5 x8.5 mm�� with 45214 transistors . The decoder has achieve a maximum datathrouthput rate in the range of 656 Kbit/s and 1750 Kbit/s with a net codinggain of 5.6 dB (at 10�笐� bit error rate ). |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。