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題名 | The C-V Hysteresis Phenomena in Aluminum/Tantalum Oxide/Sillicon Oxide/Silicon Capacitors Due to Leakage Property of Tantalum Oxide and Negative Charge Temperature Effect=氧化鉭層漏電特性和負電荷溫度效應對鋁/氧化鉭/二氧化矽/矽結構電容器C-V磁滯現象的影響 |
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作者 | 鄭明哲; | 書刊名 | 新埔學報 |
卷期 | 13 1994.12[民83.12] |
頁次 | 頁64-99 |
分類號 | 448.115 |
關鍵詞 | 氧化鉭層; 漏電; 負電荷; 溫度效應; 鋁; 氧化鉭; 二氧化矽; 矽; 電容器; C-V磁滯現象; |
語文 | 英文(English) |
英文摘要 | The C-V hysteresis phenomena in the capacitors consisting of tantalum oxide layers was studied by postmetallization annealing and meastrement conditions. It was found that the magnitude of the hysteresis loops is sensitive to measurement conditions such as the return voltage, the hold time (at return point) and the sweep rate of VG. The direction of the hysteresis loops depends on postmetallization annealing temperature. A model consisting of the leakage property of tantalum oxide and the generation of slow trap states at the silicon oxide/silicon interface due to negative charge temperature effect was proposed in this work, and explained the observation quite well. It is believed that for a MTOS(P) capacitor the clockwise C-V hysteresis loop or for a MTOS(n) capacitor the counterclockwise C-V hysteresis loop is caused by the leakage property of tantalum oxide, and for a MTOS(P) capacitor the counterclockwise C-V hysteresis loop or for a MTOS(n) capacitor the clockwise C-V hysteresis loop is caused by negative charge temperature effect at silicon oxide/silicon interface. |
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