頁籤選單縮合
題名 | 使用FPGA實現16×16高速乘法器 |
---|---|
作者 | 游竹; | 書刊名 | 宜蘭農工學報 |
卷期 | 9 1994.12[民83.12] |
頁次 | 頁113-129 |
分類號 | 310.153 |
關鍵詞 | Wallace-tree乘法器; 前瞻加法器; 進位選擇; (5,5,4)計數器; (2,2)計數器; FPGA; Wallace-tree multiplier; Carry select; Carry look-ahead adder; (5,5,4)counter; (2,2)counter; |
語文 | 中文(Chinese) |
中文摘要 | FPGA(Field Programmable Gate Array)是在1985首先由XILINX公司推出之後, 許多廠家也加入製造各種規格的 FPGA IC,這使得原 FPGA 的邏輯閘總數( gate count ) 越來越大, 速度越來越快更加實用, 以前要做用龐大的組合邏輯電路,現在幾乎只要一顆 FPGA 即可取代, 並且由於 FPGA 可重複程式內部的資料路徑,使得非常適合在實驗室裡發 展,以便節省開發費用減少金錢浪費及縮短發展時間爭取時效。 本乘法器算法主要是使用 16 × 16 Wallace-tree 結構,部分積的點數大小規劃, 是採用 ( 5,5,4 )計數器及( 2,2 )計數器, 整個乘法器共使用 41 個( 5,5,4 )計數器兩個 ( 2,2 )計數器, 在最後一級的兩點數相加是使用進位選擇( carry select )前瞻加法 器( Carry Look-ahead Adder ), 這使得整個乘法器計算速度加快許多, 如果選用 XILINX 公司之 XC4013-4 FPGA,則本乘法器的計算速度近似值為 77.3ns,若以此速率已能 夠處理大部分的數位信號,達到快速計算的能力。 |
英文摘要 | The FPGA (Field Programmable Gate Array) was first manufactured by XILINX in 1985, and after then various kinds of FPGA IC with different specifications had been produced by some other companies. Because of the increasing of gate count and improvement of performance, FPGA became more practical. Instead of using lots of combinational logic circuit, one shall only employ a single FPGA chip to do the processing. In addition, FPGA can also duplicate programmable internal data path; this makes it suitable to be developed in Lab, and at the same time it saves research fees, shortens the period needed for entire project as well. The multiplier algorithm adopts a 16 × 16 Wallace-tree structure, and the management of grid size of partial product is carrying out by (5,5,4) and (2,2) counters. The multiplier includes a total of forty-one (5,5.4) counters and two (2,2) counters. A carry-select carry-look-ahead adder is employed at the last stage for the purpose of two-grid addition. The speed of multiplier has been increasing by using the preceding algorthm. If the XC4013-4 FPGA from XILINX is chosen, the speed of above multiplier approximates to 77.3ns. Therefore, the problem of consuming too much processing time dealing with digital signals has been resolved. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。