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題 名 | Increased Swing BiNMOS/CMOS Buffer and Inverter Circuit for Low-Internal-Voltage ULSI System=低內電壓ULSI系統上增幅BiNMOS/CMOS緩衝器與反向器電路 |
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作 者 | 王清松; | 書刊名 | 亞東工業專科學校學報 |
卷 期 | 19 1999.06[民88.06] |
頁 次 | 頁(7)1-(7)6 |
分類號 | 448.57 |
關鍵詞 | 低內電壓; ULSI系統; 緩衝器; 反向器電路; |
語 文 | 英文(English) |
中文摘要 | 本文提出在低功率ULSI系統上新的BiNMOS增幅緩衝器(ISB)及BiNMOS/CMOS增 幅反向器(ISB),只要Vint>|Vt|(設Vtn=-Vtp),本電路能在低電壓及低輸入信號電壓下正 確工作,在相同面積下,亦比另一[4]提出電路具較低內外電壓比值(Vint/Vext)。BiNMOS 電路適合於高速工作,CMOS反向器亦比[4]電路較少電路面積特性,並在相同電路面積比較 下,負載電容不大於0.1pf時,本文電路具有傳送延遲少21%,功率消耗省13%之優點。本 文亦建立電路面積Kr=Kn/Kp之關係式,方便為減少功率消耗下容易設計出電路尺寸的大小。 |
英文摘要 | In this paper a new BiNMOS increased swing buffer (ISB) and a new BiNMOS/CMOS increased swing inverter (ISI) for low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can be operated at low internal voltage (Vint) and have low input signal swing. As long as Vint>|Vt| (assuming Vtn=-Vtp), the circuits can work properly. The lower bound of the voltage ratio Vint/Vext of the proposed circuits is less than that of the circuit in [4] under the same area condition. The BiNMOS circuit is suitable for high-speed operations. The new CMOS ISI circuit takes less area and furthermore, when the capacitor load is less than 0.1pf, the propagation delay is reduced by 21% and the power consumption is reduced by 13% compared with the previous circuits under the same circuit design parameters. We also establish the relationship of the Kr=Kn/Kp ratio to the circuit area and this can avoid the trial and error step in the circuit sizing operation to reduce the power consumption. |
本系統中英文摘要資訊取自各篇刊載內容。