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題名 | 單一時脈二進位正整數除法器設計 |
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作者 | 謝金石; | 書刊名 | 技術學刊 |
卷期 | 3:1 1988.03[民77.03] |
頁次 | 頁33-39 |
分類號 | 448.595 |
關鍵詞 | 二進位; 正整數; 除法器; 設計; |
語文 | 中文(Chinese) |
中文摘要 | 計算機的算術邏輯單元在執行除法運算時,若為一般情況以二個時脈執行一個位元的運算,則需較長的執行時間。一部十六位元的計算機需要三十三個時脈才能完成一個除法。本研究報告係設計一個除法器,於單一時脈內執行二進位正整數除法,所用理論是依不恢復性除法 (non-restoring division) 原理設計。由於本研究報告只探討正整數範圍,故其除數和被除數均須為正整數,如果n位元路法器,則被除數最大值是2n-1,除數最大值是2n-1-1。在本研究報告中以四位元除法器為討論範例。 |
英文摘要 | Generally, the arithematic logic unit of a computer performing division operations needs a longer time if the performance of the one-bit operation needs two cycles. For example, thirty two cycles are needed to perform division in a 16-bit computer. The purpose of this paper is to describe a diviser which performs the division of binary positive integers in one cycle. The design is based on the theory of algorithm of non-restoring division. Since this paper only discusses positive integers, the divisor and the dividend must both be positive integers. For an n-bit diviser, the maximum dividend is 2n-1 and the maximum divisor is 2n-1-1. A 4-bit divriser is used for examples in this paper. |
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