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題名 | 低電壓低頻率之微處理器系統=A Low-Voltage Low-Frequenc Microprocessor System |
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作者 | 溫穗安; 唐偉翔; 陳峻志; 林耿裕; 佟興无; | 書刊名 | 電腦與通訊 |
卷期 | 152 2013.08[民102.08] |
頁次 | 頁87-93 |
專輯 | 數位IC設計技術專題 |
分類號 | 448.5 |
關鍵詞 | 微處理器; 功率消耗; 功耗性能比; Microprocessor; Power consumption; Power performance ratio; |
語文 | 中文(Chinese) |
中文摘要 | 系統單晶片設計最大的技術挑戰之一,在於如何降低系統功率消耗,過高的功率消耗會影響系統效能與可靠度。當電晶體操作在接近臨界電壓時,藉由貫通電流減少與操作電壓的下降,可以同時降低電路動態與靜態功率消耗;而此低電壓、低頻率的系統用於不需要即時高速運算的情境,更能凸顯其節能省電的特性。本文章主要內容是介紹以65奈米超低電壓數位標準元件庫所開發的一個低功耗32位元微處理器-SPARK,實做驗證具低操作電壓特色之微處理器系統,並探索此系統之功耗效益。實驗數據資料顯示,SPARK微處理器工作電壓在0.4伏特/5.5MHz,功耗性能比為34.91μW/MHz;當系統操作頻率設定在1MHz時,與操作電壓在1.2伏特相比,0.4伏特操作電壓可以延長6倍電池的使用時間。 |
英文摘要 | How to reduce power consumption is a real challenge on SoC design. Huge energy dissipation affects system performance and reliability. By making CMOS transistors operate at near-threshold voltage, both dynamic and static power are reduced to lower levels due to the decrease of shoot-through current and minimized supply voltage. For application scenarios without high computational requirements, low-voltage low-frequency systems manifest their energy-saving characteristics. In this paper, we develop a low-power consumption 32-bit microprocessor, SPARK, with a 65nm LP process and ultra-low voltage digital standard cell library to implement a microprocessor system for the exploration of its power consumption efficiency. According to the experimental results, the best power performance ratio of SPARK is 34.91μW/MHz. When the system operating frequency is fixed at 1MHz, the battery life extends 6 times longer when the operating voltage changes from 1.2V to 0.4V. |
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