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題 名 | Multi-Bank Reorder Buffer to Support High Issuing and Retiring Rate for Superscalar Microprocessors=超純量微處理器中支援高指令發出率與完成率之多組庫重排序緩衝器 |
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作 者 | 黃樹林; | 書刊名 | 明志學報 |
卷 期 | 38:2 2007.01[民96.01] |
頁 次 | 頁51-59 |
分類號 | 471.62 |
關鍵詞 | 超級純量; 重排序緩衝器; 多組庫; Superscalar; Reorder buffer; Multi-bank; |
語 文 | 英文(English) |
中文摘要 | 超級純量微處理器大多支援預測式平行執行以提升系統效能,這代表指令能被亂序執行。因此需要一個能重新排列指令為原始程式中順式的機制以保持正確的程式狀態。另一方面,當指令被亂序執行時也需能提供暫存器改名機制以解決資料相依問題(WAR 或WAW)。一個重排序緩衝器通常在達成這兩個需求中扮演重要的角色。本論文主要提出一個於超級純量微處理器中能達到高指令發出率與完成率(最高為 8個固定長度的 RISC 指令或稱為微運算碼)的重排序緩衝器的設計。並且為了簡化切換及讀/寫埠的複雜度,全部的資料位置使用交錯方式被分成八個獨立的組庫來運作。 |
英文摘要 | Surerscalar microprocessors mostly support for speculative parallel execution to enhance system performance, this methodology means the instrutions can be out-of-order executed. A mechanism is required for rearranging the instrution in orginal program sequence to keep a correct state. Another requirement, the register renaming mechanism is provided for resolving data dependence (WAR or WAW) when the instructions are executed out-of-order. A Reorder Buffer plays the role for achieving these two requirements. This paper proposes a desigh of high issuing and retiring rate (up to eight fixed-length RISC instructions referred to as micro-ops) Reorder Buffer of a superscalar microprocessor. In order to reduce the complexity of switching and read/write ports, the total entries are divided into eight independent banks by an interleaved way. |
本系統中英文摘要資訊取自各篇刊載內容。