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題 名 | 電信同步量測系統之開發與可行性評估=The Development and Feasibility Evaluation of the Telecommunications Synchronization Measurement System |
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作 者 | 黎明富; 廖嘉旭; | 書刊名 | 電信研究 |
卷 期 | 34:6 2004.12[民93.12] |
頁 次 | 頁633-648 |
分類號 | 448.6 |
關鍵詞 | 網路同步; 穩定度; 擾動; 漂移; 鐘訊回復電路; Jitter; Wander; Clock recovery circuit; ADEV; Allan deviation; MTIE; Maximum time interval error; TDEV; Time deviation; MDEV; Modified allan deviation; |
語 文 | 中文(Chinese) |
中文摘要 | 電信網路之同步效能對傳輸品質有相當程度的影響,為了確保網路的傳輸品質,必須定期地對網路做同步性能的查測,在網路同步量測中,常使用的評估參數包括電信時鐘的穩定度(Stability)、時脈信號(Timing)的擾動(Jitter)與漂移(Wander)。擾動指的是待測時脈信號與標準時脈信號的相位差(Phase Error),而漂移則是指時脈信號的長期頻率變化狀況,其主要參數包括最大時間間隔誤差MTIE(Maximum Time Interval Error)及時間偏差TDEV(Time Deviation),他們均定義在ITU-T的規範中。一般電信同步信號的量測是先將電信網路之數據信號透過一鐘訊回復電路(Clock Recovery Circuit)將數據信號轉成時脈信號,再將此時脈信號輸入到時間間隔計數器(Time Interval Counter)與標準頻率信號做比對,測出其相位差輸出。然此種方法必須使用一鐘訊回復電路,對不同速率的網路,其量測設備都不同,無形中增加了量測設備的成本。基於這樣的考量,我們將提出一種新的架構,此架構是利用軟體來取代鐘訊回復電路的功能,也就是說我們可直接將數據信號輸入到時間間隔計數器來做量測,如此一來,我們便可利用現成的設備,如PC及時間間隔計數器,或者自行開發新的量測設備來做電信同步量測,這樣便可大大地降低量測設備的成本,並提高設備的便利性與適用性。然而,此新架構必須經過嚴謹與適當的驗證方為可行,本文將透過相位雜訊的模擬分析來驗證此新架構的正確性與可行性。 |
英文摘要 | Telecommunications synchronization has a significant effect on the quality of network transmission. To guarantee the quality of transmission, it is necessary to conduct the network synchronization auditing periodically. For network synchronization measurement, the frequently used evaluation parameters include the lock stability, jitter and wander of timing signal. Jitter is the phase error between the measured timing signal and the standard reference frequency, while wander represents the long-term frequency variations of the timing signal. The key parameters of wander consist of MTIE (Maximum Time Interval Error) and TDEV (Time Deviation) which are defined in ITU-T recommendation. Usually, in the telecommunications synchronization measurement the data signal must be converted to the timing signal via the clock recovery circuit at first. Secondly, the recovered timing signal is then input to the time interval counter for phase comparison with the standard reference frequency. In this conventional method, a clock recovery circuit should be employed. For different speed network, different measurement instrumentation is used. Hence, the measurement cost is increased. In order to improve this drawback, we will propose novel measurement architecture. In the proposed architecture, the clock recovery circuit is replaced by software so that the data signal can input to the time interval counter directly without any conversion. Therefore, we can just use the available PC and time interval counter or develop a new instrumentation to do network synchronization measurement. It can reduce the measurement cost significantly and enhance the measurement convenience. However, the new archtiecture must be demonstrated properly before it can be implemented. In this paper, we will use the phase noise simulation scheme to verify the proposed architecture. |
本系統中英文摘要資訊取自各篇刊載內容。