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題名 | An 800 Mb/S Tracking Clock Recovery Receiver for the IEEE P1394a Serial Bus=一適用於IEEE P1394a序列傳輸追蹤式時脈及資料回復接收機 |
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作者姓名(中文) | 張湘輝; 鄧光鎧; 劉深淵; | 書刊名 | 國立臺灣大學工程學刊 |
卷期 | 88 2003.06[民92.06] |
頁次 | 頁87-96 |
專輯 | 「電機工程」專輯 |
分類號 | 448.532 |
關鍵詞 | 資料與時脈回復電路; 延遲鎖相迴路; 鎖相迴路; Data and clock recovery circuits; Delay-locked loop; Phase-locked loop; |
語文 | 英文(English) |
中文摘要 | 本論文提出一適用於IEEE P1394a序列傳輸追蹤式時脈及資料回復接收機。這接收機利用超取樣技術來避免亞穩(metastable)問題,同時使用一數位相位移轉器來增加對雜訊抵抗力。循環式相位調整機制使得在時脈及資料的時間上歪斜校整動作可以獨自運作。這原型電路實現在一 0.25mm 2P4M CMOS製程,所佔的面積為740 × 1850mm2。當電路操作在2.5伏特電壓下及800Mb/s所消耗的功率為85mW。當資料通過一4.5公尺長的IEEE P1394a序列傳輸線,這接收機量測到的錯誤率(BER)小於十的負十次方(10-10)。 |
英文摘要 | A tracking clock recovery receiver for the IEEE P1394a high performance serial bus is presented in this paper. The proposed tracking receiver utilizes an oversampling technique to avoid the metastable problem and a digital phase shifting approach to improve the noise immunity, compared to the analog one. The cyclic phase adjusting mechanism makes the operation independent of the intrinsic timing skew between clock and data channels. Fabricated in a 0.25mm 2P4M CMOS process, the prototype chip dissipates a power of 85mW at 2.5V supply voltage when the data rate is 800Mb/s and occupies 740 × 1850μm2. After the data stream is propagated through a 4.5m IEEE P1394a serial bus, the measured BER is less than 10-10. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。