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題 名 | A Synthesizer for Infinite Nested Loops Under Timing/Cost Constraints=一個在時間成本限制下之無限巢狀式迴路之自動合成系統 |
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作 者 | 蔣元隆; 楊正宏; 鐘國家; 陳聰毅; 蔡南隆; | 書刊名 | 高雄應用科技大學學報 |
卷 期 | 31 2001.12[民90.12] |
頁 次 | 頁123-139 |
分類號 | 448.532 |
關鍵詞 | 無限巢狀式迴路; 合成電路; Synthesizer; Pipelined data paths; Infinite nested loops; Mapping algorithms; |
語 文 | 英文(English) |
中文摘要 | 在這篇論文中,我們提出一種新技術來合成電路,其輸入為C語言程式含巢狀式迴路且含條件跳躍。此合成技術且可在時間及成本限制下作最佳化。在本文中,我用數論的技巧提出一簡單之定理,可避免耗費許多之電腦時間,即可獲得最佳解。實驗結果証明,本文所提之技術比過去所提之論文都好,連結線將因此大幅度減少,這對深次微米時代是非常重要的。 |
英文摘要 | Is this paper, a new technique is presented to synthesize pipelined data paths for those C programs containing infinite nested loops with conditional branches under timing/area constraints. Given a C program, an initiation interval, a number of function units for each type of operations and the minimum length of the clock cycle, the objective is to synthesize a data/control path for the problem under the given constraints. Based on our previous work in [23], we first schedule the conditional instructions such that the maximal sharing can be made in the following steps. Then, we present a simple criterion to predict the sufficiency of the given function units. If the given constraints are sufficient, we present a new approach which conserves the regularities of nested loops such that the scheduling and the allocation efforts can be greatly minimized and the result is a lowly multiplexed architecture. Mapping algorithms for systolic array synthesis which do not take initiation interval into account cannot be applied to our case; while traditional pipeline synthesis techniques suffer from complex interconnection and high register cost. Experiments on several algorithms in the image and DSP applications show this approach is very efficient. |
本系統中英文摘要資訊取自各篇刊載內容。