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題 名 | DSP-based ADSL傳收機前置電路設計與模擬=Design and Simulation of DSP-based ADSL Transceiver Front End Circuit |
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作 者 | 陳信溢; | 書刊名 | 電信研究 |
卷 期 | 31:4 2001.08[民90.08] |
頁 次 | 頁449-461 |
分類號 | 448.532 |
關鍵詞 | 傳收機前置電路; ADC; Analog to digital converter; ADSL; Asymmetrical digital subscriber line; AFE; Analog front end; AGC; Automatic gain control; ATU-C; ADSL transceiver unit, central office end; ATU-R; ADSL transceiver unit, remote terminal end; DAC; Digital to analog converter; DMT; Discrete multitone; TX; Transmit; RX; Receive; |
語 文 | 中文(Chinese) |
中文摘要 | DSP-Based ADSL傳收機前置電路包含了類比前置電路與數位訊號處理介面電路的 功能。為了因應傳輸線的高衰減現象,並保持訊號在可接受的訊號雜訊比,類比前置電路扮 演著重要的角色,它限制了整個系統的性能,且亦影響到數位電路的參數設計。由於數位訊 號處理器與類比前置電路間的資料傳送速度與格式不相同, 因此傳送資料必須要經以 FPGA 晶片實現的數位電路做多工、取樣、緩衝處理。在本文內,我們將詳細討論上述電路的設計 與模擬結果。 |
英文摘要 | DSP-Based ADSL Transceiver Front End Circuit contains both the analog front end circuit and digital signal processing interface circuit function blocks. In order to cope with the high attenuation of the line and maintain acceptable signal to noise ratio (SNR), the analog front end circuit takes an import role. It also dominates the performance of the whole system. Furthermore, many parameters of the digital part depend on the circuit design of the analog front end. Since the data transmission speed and formats are different between digital signal processor and analog front end circuit, it should be multiplexed, sampled, and buffered by using specifically designed FPGA Chip. In this paper, we discuss the circuit design and simulation results in detail. |
本系統中英文摘要資訊取自各篇刊載內容。