頁籤選單縮合
題 名 | A Study of the Hardware-based Data Prefetching Technique for Pipeline Processor=以硬體為基礎的管線式處理器之資料預取技術研究 |
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作 者 | 杜日富; | 書刊名 | 泰山職訓學報 |
卷 期 | 4 2001.04[民90.04] |
頁 次 | 頁282-298 |
分類號 | 471.61 |
關鍵詞 | 硬體; 管線式處理器; 資料預取; Data prefetching register; DPB; Data reuse register; DRR; Prefetching miss; Prefetching hit; |
語 文 | 英文(English) |
英文摘要 | This paper proposes a method for improving the data prefetching performance in the RISC processor. In this paper, we introduce a new data prefetcher that contains an instruction recognizer (IR) and data prefetching register. The fore is combined the instruction register, comparison, and the previous table; the latter being a combination of a data reuse register and a data prefetching register. We build an adaptive data prefetcher with the intention of reducing the need data accessing latency time and of improving the processor performance. A simulation is run and data are gathered both trace from Arena. The evaluation results in terms of the throughput show that the new data prefetcher is more effective than the traditional one pipeline processor on average. For the ADP architecture, the throughput improvement is 1.32 times to the latter one. |
本系統中英文摘要資訊取自各篇刊載內容。