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題名 | 非同步傳輸網路卡的設計與製作=Design and Implementation of a High Speed ATM Network Interface Card |
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作者 | 邱孟希; 張慶龍; 楊順欽; 侯廷昭; 朱元三; | 書刊名 | 技術學刊 |
卷期 | 15:1 2000.03[民89.03] |
頁次 | 頁187-193 |
分類號 | 448.6 |
關鍵詞 | 非同步傳輸模式; 網路卡; 現場可程式規劃邏輯閘陣列; Asynchronous transfer mode; Network interface card; FPGA; |
語文 | 中文(Chinese) |
中文摘要 | 在以碼格(Cell)為基礎的非同步傳輸(ATM)網路環境中,欲傳送或接收的資料 必須快速的處理以符合高速需求。而此以碼格為單位的協定處理,若以主機( Host )軟體 來處理會消耗大量中央處理器( CPU )的時間,也會增加軟硬體間的通信負荷, 因此最好 用硬體作 ATM 層協定的處理。 我們在個人電腦( PC ) PCI 匯流排的環境中, 成功發展出具有光纖介面的 100Mbps ATM 網路卡。 為了讓網路卡得以較低的 12.5MHz FPGA 系統時脈支援 100Mbps 的傳輸需求,我 們發展了一個遞迴並行冗餘核對( CRC )之演算法來設計 ATM 層的 HEC 及 AAL5 的 CRC-32, 此演算法可適用於任何資料長度的 CRC 計算,突破了其他演算法中資料長度必須 是平行運算位元組倍數的限制,此演算法並已獲得臺灣與美國的發明專利。 在這個網路卡上, 以三顆 FPGA 實現 ATM 和 ATM 第五適應層( AAL5 )以及 PCI 控制器 的功能。 傳送晶片透過管線( pipeline )的實現方式去除了儲存再轉送( store and forward )的時間延遲;接收端晶片實現了不同連線的記憶體管理;PCI 晶片是以自行設計 的 FPGA 完成,大幅提昇了主機與網路卡間通訊的頻寬。這三顆晶片的設計理念是以如何提 昇整個非同步傳輸終端系統的效能為考量。另外為了使乙太網路上的許多網路應用程式能夠 運作, 我們並設計 ATM 網路卡的封包驅動程式, 成功地在 DOS, Windows3.1 以及 Windows95 平臺上執行。 |
英文摘要 | In the cell-based ATM network environment, the data must be fast processed to take advantage of the underlying huge transmission bandwidth. It is not practical to use software for cell-based protocol processing because of the high cell rate and the heavy communication overhead between software and hardware; all cell-based processing ought to be done in hardware. We have conducted an ATM/TAXI interface card design for the PCI-based PC host. The goal is to build a high-speed communication interface that performs all cell-based protocol processing. In order to utilize the full band-width of the 100Mbps TAXI interface using the 12.5 MHz system clock of ATM/AAL5 NIC, a recursive parallel CRC algorithm is proposed and implemented for AAL5 and the HEC generation in the ATM header in our ATM chips. Other parallel CRC algorithms require the length of the processed data be an integer multiple of the parallel operation length. Our algorithm relieves the above constraint and has been granted Taiwan and USA patents. Three FPGAs that support the PCI controller and the ATM/AAL5 functions are implemented. Transmitter FPGA eliminates store-and-forward delay via pipeline operation. Receiver FPGA implements the buffer management for individual virtual connections. PCI chip is designed by ourselves and it maximizes the communication bandwidth between the host and the network interface card. The goal of the design considerations above is to improve the performance of the host with the ATM/AAL5 network interface card. An ATM device driver, which is compatible with the Ethernet packet driver, is also developed. Therefore, the ATM NIC can support all applications that run in DOS, Windows3.1 and Windows95 environments. |
本系統之摘要資訊系依該期刊論文摘要之資訊為主。