頁籤選單縮合
題 名 | Design of ATM Switch Using Novel Input-Output Queueing Architecture |
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作 者 | 李俊堅; | 書刊名 | 華夏學報 |
卷 期 | 34 1999.12[民88.12] |
頁 次 | 頁14297-14314 |
分類號 | 448.6 |
關鍵詞 | Broadband ISDN; Asynchronous transfer mode; Baseline network; Self-routing property; Switching; |
語 文 | 英文(English) |
英文摘要 | In this paper we propose an ATM switch for the broadband 1SDN. The basic fabric of the proposed switch consists of several baseline networks [21] in parallel to reduce the internal contention probability. A new input queueing architecture is applied to each input port controller to reduce the head of the line blocking probability. A novel output queueing architecture is used to resolve the output contention. The proposed switch operates based on a double-phase control algorithm and is a successful pipeline application. Owing to the recursive structure of baseline networks, the proposed switch has the feature of modularity and is easy for expansion. Although several paths exist between each input-output pair, the proposed switch preserves the cell integrity simply by means of a skewing operation at the input terminals of the output port. Thus, the resequence mechanism is not required in the outputs of the proposed switch. Performance evaluation of the proposed switch will appear in the buddy paper [11]. |
本系統中英文摘要資訊取自各篇刊載內容。