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題 名 | Test Energy Minimization for C-Testable ILAs |
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作 者 | 黃世安; 吳誠文; | 書刊名 | Journal of Information Science and Engineering |
卷 期 | 15:6 1999.11[民88.11] |
頁 次 | 頁899-911 |
分類號 | 312.74 |
關鍵詞 | Built-in self-test; C-testability; Design for testability; Iterative logic array; Logic testing; Test energy minimization; |
語 文 | 英文(English) |
英文摘要 | We consider energy consumption during testing for C-testable iterative logic arrays (ILAs). We show that the cell test sequences in the ILA have a property of repetition and ensure that the test energy depends on the order of the test patterns, which is obvious for random logic, but is not for ILAs due to its iteration property. The time complexity for obtaining the transition energy of all possible pattern sequences is reduced from O(X �� N �� C �� )to O (X �� C �� ), where X, N, and C represent the test length, array size, and cell complexity, respectively. We formulate the problem of finding the optimal test sequence, as a shortest-path problem. Using the obtained test sequence the total energy consumption is minimized, and the transition power is within the design specification. The time complexity is independent of the array size. |
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