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題名 | Compilable Architecture for a Reed-solomon Decoder=有compilable架構之Reed-Solomon解碼器 |
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作 者 | 陳宏偉; 吳錦川; 黃國昇; | 書刊名 | Journal of the Chinese Institute of Electrical Engineering |
卷期 | 6:3 1999.08[民88.08] |
頁次 | 頁249-257 |
分類號 | 448.5 |
關鍵詞 | 前向錯誤訂正; 可編譯架構; Reed-solomon碼; 歐幾里德演算法; FEC; Compilable architecture; Reed-solomon code; Euclid's algorithm; |
語文 | 英文(English) |
中文摘要 | 本文提出一個具有可編譯(compilable)架構,且有erasure功能之Reed-Solomon code (RS code)解碼器,並撰寫了一個編譯程式可以自動產生所需的解碼器的Verilog code。可編 譯的架構使用佈局形狀規則的電路模組,使得解碼器的面積小,而且速度快。可編譯的架構 使用不同錯誤訂正能力之解碼器可以快速的設計出來因而降低設計成本。歐幾里德演算法被 用來解主要方程式(Key equation)且硬體複雜度在主要單元(Key Unit)上得以降低一半。閘總 數(Gate count)約為傳統解碼器的60%,硬體複雜只和錯誤訂正能力有關。且有erasure功能, 其錯誤訂正能力是無erasure 功能的兩倍。利用我們的編譯程試,一個具有錯誤訂正能力為 5的實驗晶片以0.6umCMOS技術設計及製造。它的核心部份面積佔了3.135×3.452mm□。 這個晶片經以1MS-200tester測試功能正常,5伏下最快工作頻率為60MHz。 |
英文摘要 | A Reed-solomon (RS) decoder having compilable architecture and erasure function is designed and implemented. A compiler is also written which can automatically produce the needed Verilog code. To achieve compilable architecture, circuit modules with regular layout shape and connection are used which result in a small die area and a high operating speed. With compilable architecture, a decoder with different error correcting abilities can be designed in a short time to reduce design cost and time to market. A modified Euclid's algorithm is used to reduce the hardware required for solving the RS code's key equation by a factor of 2. The total gate count of the decoder is reduced to 60% of that of a conventional decoder, and the hardware complexity depends on only 2t, which is the number of parity check bytes. Its error correcting ability is t and 2t bytes/block with and without erasure function, respectively. Using the RS decoder compiler, an experimental chip with t=5 is fabricated in a 0.6 um CMOS technology, the chip's active area is 3.135*3.452 mm□. This chip is tested on an IMS-200 tester and is fully functional. The measured maximum operation frequency is 60 MHz with a 5V supply. Due to the regularity and connectivity of the circuit modules, the die area is small and operating speed is fast. |
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