頁籤選單縮合
題 名 | MX3 Multiplexer Design and Implementation=混合型第三階數位訊號多工器之設計與製作 |
---|---|
作 者 | 郭昭宗; 王敦弘; 陳重偉; 薛敏琪; 吳國棟; | 書刊名 | Journal of the Chinese Institute of Electrical Engineering |
卷 期 | 6:3 1999.08[民88.08] |
頁 次 | 頁231-239 |
分類號 | 448.6 |
關鍵詞 | 現場可程式邏輯陣列; 多工器; 時閃; FPGA; Multiplexer; Jitter; |
語 文 | 英文(English) |
中文摘要 | 在傳輸系統中,由於北美系統與歐洲系統在數位訊號階層上的差異,使得此兩大 系統間的互連顯得迫切需要。本文的主旨是以三顆現場可程式邏輯陣列為基礎來實現混合型 第三階數位訊號多工器。文中詳述混合型第三階數位訊號多工器之硬體架構和韌體架構,以 及各個電路板的功能。系統的整合測試證明是可行的。 |
英文摘要 | Since the digital signal hierarchies in North America and Europe (ITU-T Standard) are different, interworking between North American and European digital hierarchies are needed. Based on ITU-T G.747 recommendation, three E1 tributaries can be multiplexed into a DS2 signal for hierarchy interworking in the design of an MX3 multiplexer. Three multiplexer FPGA's are designed: (1) M12 (DS1 to DS2 Mux), (2) ME12 (E1 to DS2 Mux) and (3) M23 ( DS2 to DS3 Mux), as the building blocks for the MX3 Multiplexer. The MX3 multiplexer incorporates DS1 and E1 tributaries as low speed inputs and multiplexes them into a DS3 signal. Low speed, high speed, switch and system control units are designed and implemented. Firmware is designed in the system controller for integration and testing. |
本系統中英文摘要資訊取自各篇刊載內容。