頁籤選單縮合
題名 | Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors |
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作者 | 黃穎聰; 黃哲修; | 書刊名 | Journal of Information Science and Engineering |
卷期 | 14:1 1998.03[民87.03] |
頁次 | 頁139-165 |
專輯 | Special Issue on Compiler Techniques for High-Performance Computing |
分類號 | 312.49 |
關鍵詞 | Code generation; Compiler; Digital signal processors; Instruction scheduling; Memory assignment; Register allocation; Simulated evolution; |
語文 | 英文(English) |
英文摘要 | Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules must be observed to achieve full performance. These include efficient multi-operands accesses, smart use of data and address registers, and novel instruction scheduling to support parallel execution without pipeline conflicts. In this paper, an iterative codegeneration scheme based on the framework of simulated evolution is devised. Ineach iteration, the instruction scheduling derived from the previous iteration isfirst evaluated. The inferior part is probabilistically discarded and rescheduled. On the other hand. register allocation and memory assignment are also performed iteration-wise subject to the new schedule, and the results are fed back to the next iteration's instruction scheduling. This can effectively solve the mutual dependence problem between the scheduling and allocation phases. The iteration processproceeds until a valid schedule is derived. To make the system retargetable, we have also derived and summarized coding constraints from various digital signalprocessor architectures. Basic resolutions to these constraints are proposed andhave been successfully integrated into our code generation scheme. In our implementation, we chose the TI TMS320C30 as the target processor. The results ofeleven tested benchmark programs, covering algorithms from filtering to transform computation, indicate that our scheme can double the performance of TI's complimentary C30/40 optimizing C compiler in terms of code size and can generate very efficient assembly codes. |
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