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題 名 | Identification of Robust Untestable Path Delay Faults=嚴謹式非可測路徑延遲障礙之判定 |
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作 者 | 吳文慶; 李崇仁; 陳竹一; | 書刊名 | 中國工程學刊 |
卷 期 | 20:5 1997.09[民86.09] |
頁 次 | 頁549-559 |
分類號 | 448.5 |
關鍵詞 | 路徑延遲障礙; 嚴謹式延遲測試; 非可測障礙; Path delay fault; Robust delay testing; Untestable fault; |
語 文 | 英文(English) |
中文摘要 | 本論文提出一套判定嚴謹式非可測路徑延遲障礙的理論分析。首先將路徑的分合 形式歸納成七種,並推導每一種分合形式的嚴謹測試條件,據以提出路徑延遲障礙的非可測判 方法。本方法適合以電路切割形式作分散式處理,能夠節省時間和記憶體。將此方法應用到 ISCAS'85標準電路作實驗,結果顯示非可測路徑延遲障礙所佔的比例非常高,而分散式處理 能使速度提高數倍。此外,本論文也提出一種快速的非可測路徑延遲障礙的數目估算法。 |
英文摘要 | This paper presents a theoretical analysis to identify robust untestable path delay faults. Firstly, it classifies the reconvergence of paths into seven cases and deduces the necessary conditions to robustly test path delay faults for each case. It then proposes a procedure, based on the deduced conditions, to identify the robust untestable path delay faults. The procedure is suitable for distributed processing by circuit partitioning to reduce the computation time and required memory. Experimental results on ISCAS 85' benchmark circuits show that the robust untestable faults occupy a high percentage of the total faults and high speedup can be obtained for distributed processing. In addition, it also presents a method to estimate the number of robust untestable path delay faults for a circuit. |
本系統中英文摘要資訊取自各篇刊載內容。